WB_I2S - Host to Controller Communications
Communications between a 32-bit host processor and the WB_I2S Controller are carried out over a standard Wishbone bus interface. For a generic summary of the communication cycles involved between Host and Controller for writing to/reading from the accessible internal registers, see Wishbone Communications - 32-bit Processor to Slave Peripheral.
Table 1 summarizes how the 32-bit data word from the host processor is used by each of the internal registers.
Table 1. Values written to internal registers during a write.| Writing to... | Results in... |
|---|---|
| CONTROL | the entire 32-bit value arriving on DAT_I loaded into the Control register |
| MODE | the entire 32-bit value arriving on DAT_I loaded into the Mode register |
Table 2 summarizes the 'make-up' of the 32-bit data word that is read back from each register.
Table 2. Values read from internal registers during a read.| Reading from... | Presents (to host processor)... |
|---|---|
| CONTROL | 32-bit value currently in the Control register |
| MODE | 32-bit value currently in the Mode register |
| STATUS | 32-bit value currently in the Status register |
| TX_POINTERS | 32-bit value currently in the Transmit FIFO Pointers register |
| RX_POINTERS | 32-bit value currently in the Receive FIFO Pointers register |
When writing to the Data register, you are actually loading a value directly into the Transmit Buffer. Conversely, when reading from the Data register, you are actually retrieving a value directly from the Receive Buffer. The value loaded for transmission, or presented back to the host processor, will depend on the configured Word Width for the Controller, as specified in the Mode register (MODE5..0). For details on values sent and received, see Data Transfer Modes.