WB_I2S - Clocks

The prescaler value loaded into the WB_I2S Controller's Control register (CONTROL7..0) is used to set the Sample Rate as follows:

Sample Rate = CLK_BASE / (prescaler * 256)

The frequency of the WS signal is equal to the Sample Rate. In one cycle of WS, one sample (left + right channel) can be transmitted.

The serial bit clock (SCK) is always 64 times higher in frequency than the WS signal.

The additional serial clock (ADCK) is always 256 times the frequency of WS, irrespective of the Word Width configured for the Controller. ADCK is simply an additional 'general purpose' clock signal. Some audio devices require such a signal – for example to clock digital filters in the ADC/DAC stages. Note that if the resulting frequency of ADCK is not the same as the frequency of clock required by the audio device, you will need to source your own clock signal from another part of your circuit.