WB_I2S - Block Diagram

Figure 1 shows a high-level block diagram for the WB_I2S component.

Figure 1. WB_I2S block diagram.

The block diagram in Figure 1 represents the WB_I2S Controller when configured for operation with both Transmitter and Receiver sections. It also shows use of the alternate large hardware FIFO buffer for each section, as opposed to the small, built-in FIFO (32 x 24-bit).

Note also, that as the alternate large hardware buffer is enabled for use, the two additional registers – TX_POINTERS and RX_POINTERS – are also present, and the ADR_I line accordingly becomes 3 bits in width.

For information on the internal registers for the WB_I2S that can be accessed from the host processor, see Accessible Internal Registers.