WB_I2CM - Pin Description
Frozen Content
The following pin description is for the WB_I2CM when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The external interface signals will be made available as sheet entries, associated with the parent sheet symbol used to reference the underlying OpenBus System.
Table 1. WB_I2CM pin description.| Name | Type | Polarity / Bus size | Description |
|---|---|---|---|
| Control Signals | |||
| CLK_I | I | Rise | Wishbone system clock |
| RST_I | I | High | Wishbone system reset |
| Host Processor Interface Signals | |||
| STB_I | I | High | Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle |
| CYC_I | I | High | Cycle signal. When asserted, indicates the start of a valid Wishbone cycle |
| ACK_O | O | High | Standard Wishbone device acknowledgement signal. When this signal goes high, the Controller (Wishbone Slave) has finished execution of the requested action and the current bus cycle is terminated |
| ADR_I | I | 3 | Address bus, used to select an internal register of the device for writing to/reading from |
| DAT_O | O | 8 | Data to be sent to the host processor (valid when INT_O is asserted). |
| DAT_I | I | 8 | Data received from the host processor |
| WE_I | I | Level | Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle: 0 = Read |
| INT_O | O | High | Interrupt Signal. This line is taken High if the {{ien}} bit in the Control register is set (CONTROL.1) and the {{intreq}} bit in the Status register (STATUS.0) becomes set. The latter is set by the Controller whenever it completes its current operation. |
| I2C Bus Interface Signals | |||
| SDATA_EN | O | High | Output enable signal for the I2C data bidirectional buffer. |
| SDATAO | O | - | Serial data output. |
| SDATAI | I | - | Serial data input. |
| SCLK_EN | O | High | Output enable signal for the I2C clock bidirectional buffer. |
| SCLKO | O | - | Serial clock output. |
| SCLKI | I | - | Serial clock input. |
To simplify using the bidirectional SDATA and SCLK buses, the schematic symbol includes a bus pin for each direction, allowing them to be wired independently.