WB_I2CM - Accessible Internal Registers
Contents
The following sections detail the internal registers for the WB_I2CM that can be accessed from the host processor.
Control Register (CONTROL)
Address: 0h
Access: Read/Write
Value after Reset: 00h
This register is used to control aspects of the Controller's operation.
When writing to this register, the busy
bit in the Status register (STATUS.2) will be set.
MSB LSB | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
nack | start | stop | rd | wr | iack | ien | - |
Bit | Symbol | Function |
---|---|---|
CONTROL.7 | nack | Negative Acknowledge bit. This bit is used only when the Controller is reading data from a slave I2C device and represents the data line on the ninth clock. If set, then on the ninth clock pulse the data line will be high which is defined as NOT ACKNOWLEDGE by I2C protocol. If cleared, then the data line will be held low which is defined as ACKNOWLEDGE by I2C protocol. This is useful when reading more than one byte of data, where a slave device waits for the Controller to acknowledge that the transfer was successful, so that it can prepare to send another byte. |
CONTROL.6 | start | Start Condition bit. This bit, when set, will generate a START condition. If the |
CONTROL.5 | stop | Stop Condition bit. This bit, when set, will generate a STOP condition. When this bit is set together with the |
CONTROL.4 | rd | Read Transfer bit. This bit initates a read transfer. When set, the Controller will shift in 8-bit data from an I2C slave device. The data will be loaded into the DATA_READ register, which in turn can be read by the host processor. |
CONTROL.3 | wr | Write Transfer bit. This bit initiates a write transfer. When set, the Controller will transfer the contents of the DATA_WRITE register to an I2C slave device. |
CONTROL.2 | iack | Interrupt Acknowledge flag. This bit represents the interrupt acknowledgement that is sent from the host processor to the Controller. Once an interrupt is issued by the Controller, the host must set this bit in order to clear the |
CONTROL.1 | ien | Interrupt Enable bit. This bit enables the interrupt line to be driven by the Controller in response to transfer finish or any error that might happen on the I2C bus. If this bit is cleared the Controller will not pull the interrupt line high.
If the interrupt line is not used this bit could be used to see when the Controller has finished the requested operation. |
CONTROL.0 | - | Not Used. Returns '0' when read. |
Status Register (STATUS)
Address: 1h
Access: Read Only
Value after Reset: 00h
This register is used to determine the current state of the WB_I2CM component.
MSB LSB | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | - | - | - | busy | rxack | intreq |
Bit | Symbol | Function |
---|---|---|
STATUS.7 | - | Not Used. Returns '0' when read. |
STATUS.6 | - | Not Used. Returns '0' when read. |
STATUS.5 | - | Not Used. Returns '0' when read. |
STATUS.4 | - | Not Used. Returns '0' when read. |
STATUS.3 | - | Not Used. Returns '0' when read. |
STATUS.2 | busy | Busy flag. This bit is set while the Controller performs the requested operation. It is cleared when the Controller enters 'idle' state and waits for a command in the Control register. |
STATUS.1 | rxack | Receive Acknowledge flag. This bit represents the state of the data line at the ninth clock pulse while sending data. When it is 0 then it is considered the slave device acknowledged the transfer. If 1, then NACK was received. When sending an address this bit indicates if a slave device with the address issued is connected to the Controller or not. |
STATUS.0 | intreq | Interrupt Request flag. This bit is set by the Controller when it has finished its current operation. |
Clock Register 0 (CLOCK0)
Address: 2h
Access: Read/Write
Value after Reset: 00h
This register is used to hold the low order byte of the 16-bit value used to scale the frequency of the clock generated by the Controller. By accessing this address, you are in effect accessing bits 7..0 of the internal CLKDIV register.
Clock Register 1 (CLOCK1)
Address: 3h
Access: Read/Write
Value after Reset: 00h
This register is used to hold the high order byte of the 16-bit value used to scale the frequency of the clock generated by the Controller. By accessing this address, you are in effect accessing bits 15..8 of the internal CLKDIV register.
Data Write Register (DATA_WRITE)
Address: 4h
Access: Read/Write
Value after Reset: 00h
This register is used to contain data to be written to a slave device over the I2C Bus. It has a two-fold purpose:
- When initiating communications with a slave device, it is used to store the address of the required device. The address is stored as bits 7..1, with bit 0 used to indicate whether a Write (bit 0 = '0') or Read (bit 0 = '1') is to be performed.
- Once the required slave has been addressed, it is used to store a byte of data to be written to that device.
Data to be transmitted over the I2C Bus is loaded from the DATA_WRITE register into the internal Shift Register. During transmission, the data is sent MSB first.
Data Read Register (DATA_READ)
Address: 5h
Access: Read Only
Value after Reset: 00h
This register is used to contain data received from an addressed slave device over the I2C Bus.
Received data is shifted into the internal Shift Register. On reception of the full data byte, the data will be loaded into the DATA_READ register.