VGA32_TFT - Wishbone 32-bit VGA Controller with TFT Interface
The VGA32_TFT Controller provides a simple, 32-bit interface between a host processor and a TFT (Thin Film Transistor) LCD panel. The Controller fetches 16bpp-formatted data from external video memory, processes it and displays it on the connected TFT LCD panel. All control signals required by the panel are generated in-core, using an integrated TFT Timing Controller unit.
The VGA32_TFT has been specifically designed to operate with the TX09D50VM1CAA – an Hitachi color TFT LCD panel offering a resolution of 240x320. All timings (horizontal and vertical) have therefore been fixed, in accordance with the timing requirements of this particular panel.
Features at-a-glance
- All timings fixed to specifically suit an Hitachi 240x320 TFT panel (e.g. the TX09D50VM1CAA)
- Resolution fixed at 240x320
- Refresh rate fixed at 50Hz
- Integrated TFT Timing Controller generates all TFT panel-specific control signals
- Fixed color quality of 16bpp
Availability
From an OpenBus System document, the VGA32_TFT Controller can be found in the Peripherals region of the OpenBus Palette panel.
From a schematic document, the VGA32_TFT Controller is available by placing and configuring a WB_VGA - Configurable Wishbone Display Driver. This component can be found in the FPGA Peripherals (Wishbone) integrated library (FPGA Peripherals (Wishbone).IntLib), located in the \Library\Fpga folder of the installation.
Designing with the VGA32_TFT Controller
Use the following links to explore use of the VGA32_TFT Controller in more detail: