Improved SDRAM Controllers (AD10)

Altium Designer 10 delivers improvements to the SDRAM controller interface, available through the three configurable Wishbone memory controller peripherals – WB_MEM_CTRL, WB_SHARED_MEM_CTRL_NB2DSK01, and WB_SHARED_MEM_CTRL_NB3000. The SDRAM Controller can now be configured with optional internal caching, speeding up random memory access and giving a raw memory speed approaching that of the SRAM interface. In addition, you can now specify the refresh rate, depending on whether your connected SDRAM device(s) are Standard or Automotive grade.

Internal Caching

When configuring any of the memory controller peripherals to provide an SDRAM Controller interface, internal caching is enabled or disabled using the Include Cache option.

Option to include internal caching for an independent SDRAM controller (WB_MEM_CTRL) and a shared memory controller configured with SDRAM interface (WB_SHARED_MEM_CTRL_NB3000 shown).

Internal caching is truly transparent, and implemented as a directly-mapped cache. The burst-access feature of SDRAM memory is utilized, allowing 8 words to be prefetched at a time and stored in the cache. This allows the access cycles – as seen on the CPU Wishbone bus – to be hidden.

Internally, the cache is organized as two Block RAM memories:

• Data Memory – used to store lines (cache lines), with each line being 8 memory IC words. Depending on the width of the data port for the connected SDRAM device, the number of bytes in a cache line will vary. For 32-bit memory, there will be 8 32-bit cache words, giving a total of 32 bytes in a cache line. Similarly, for 16-bit memory, there will be 16 bytes in a cache line, and for 8-bit memory, 8 bytes.

• Tag Memory – used to store TAGS. There is one TAG (stored in the Tag memory) per cache line (stored in the Data memory). When reading or writing the cache, it is the TAG portion of the generated tag (TAG + Data memory address) that is used to verify if the data in the cache is valid for that address or not and, if it is, corresponds to that particular address in SDRAM memory.

Cache Sizing

The cache size is fixed at 2048 32-bit words. It remains this size, regardless of the size of the physical SDRAM memory you are connecting to. Depending on the SDRAM size, the number of bits used in the TAG for a cache line will vary. The width of the Block RAM used for the Tag memory is adjusted automatically, depending on this number of bits. The following table lists the various sizes of SDRAM supported by the memory controllers, and the corresponding number of bits used in a TAG.

The size of the Tag memory is also adjusted automatically to allow the storage of a number of TAGs equal to the number of cache lines in the Data memory (remember, 1 TAG per cache line). For example, a 16-bit SDRAM memory will have double the number of cache lines of a 32-bit memory, requiring the Tag memory to be doubled in size accordingly.

Tag memory sizing and width are all handled transparently for you.

Operational Overview

Talking to the cache takes a minimum of 2 clock cycles. In the first cycle, data is clocked out from both the Data memory and the Tag memory – combined to generate a 'tag address' for that particular cache line (also referred to as the 'Data cache address'). The generated tag address takes the following format:

TAG + Cache Line + Cache Word + Byte within Word

Whenever there is a read memory request on the Wishbone bus (from the processor), the TAG portion of the generated tag address is compared with the corresponding top bits of the Wishbone address. For example a 64MB SDRAM device uses 13 bits for a TAG, and these 13 bits would be compared with the top 13 bits of the ADR_I line from the processor (i.e. ADR_I[25..13]). If the two values match, then that data in cache is valid and corresponds to that particular address in the SDRAM memory. The data from the cache's Data memory is then returned to the processor on the Wishbone data bus.

Similarly for a write memory request, if the incoming TAG portion of the Wishbone address matches the TAG portion of the generated tag address for the cache, then data is committed to the Data memory of the cache.

If the TAG does not match that addressed by the processor, then this is interpreted as a 'cache miss' – the cache line holds data from another region of memory. In this case, a line replace procedure is initiated. This involves writing the current line to SDRAM memory and replacing it with new data from the target memory destination. Cache line replace strategy is optimized for latency. Data currently requested by the processor is fetched first and the Wishbone interface is released as soon as this process completes. The rest of the cache line is replaced in the background.

Using the Cache with 32-bit Memory

The following table illustrates the generated tag address when using 32-bit SDRAM memory. A 64MB SDRAM device is used, giving a 26-bit Wishbone address bus.

Tag address generation (ADR_I[25..0]):

The Tag address sent from the processor on the Wishbone address bus consists of the following:

ADR_I[25..13] – TAG stored in separate Tag memory of the cache.

ADR_I[12..2] – address in the Data memory of the cache. Bits 12..5 select the cache line, while bits 4..2 select the word from that cache line.

ADR_I[1..0] – used to select the specific byte within the cache word.

The following image illustrates Data Memory organization in the cache when using 32-bit SDRAM memory.

Cache Data memory structure (32-bit memory).

Using the Cache with 16-bit Memory

The following table illustrates the generated tag address when using 16-bit SDRAM memory. A 64MB SDRAM device is used, giving a 26-bit Wishbone address bus.

Tag address generation (ADR_I[25..0]):

The Tag address sent from the processor on the Wishbone address bus consists of the following:

ADR_I[25..13] – TAG stored in separate Tag memory of the cache.

ADR_I[12..2] – address in the Data memory of the cache. Bits 12..4 select the cache line, while bits 3..2 select the word from that cache line.

ADR_I[1..0] – used to select the specific byte within the cache word.

The following image illustrates Data Memory organization in the cache when using 16-bit SDRAM memory.

Cache Data memory structure (16-bit memory).

Using the Cache with 8-bit Memory

The following table illustrates the generated tag address when using 8-bit SDRAM memory. A 64MB SDRAM device is used, giving a 26-bit Wishbone address bus.

Tag address generation (ADR_I[25..0]):

The Tag address sent from the processor on the Wishbone address bus consists of the following:

ADR_I[25..13] – TAG stored in separate Tag memory of the cache.

ADR_I[12..2] – address in the Data memory of the cache. Bits 12..3 select the cache line, while bit 2 selects the word from that cache line.

ADR_I[1..0] – used to select the specific byte within the cache word.

The following image illustrates Data Memory organization in the cache when using 8-bit SDRAM memory.

Cache Data memory structure (8-bit memory).

Refresh Rate

When configuring any of the memory controller peripherals to provide an SDRAM Controller interface, the refresh rate is specified using the Refresh Rate option.

Option to specify the refresh rate for an independent SDRAM controller (WB_MEM_CTRL) and a shared memory controller configured with SDRAM interface (WB_SHARED_MEM_CTRL_NB3000 shown).

Select the refresh rate as required, in accordance with the type of physical SDRAM memory device you are connecting to:

• Standard – standard devices are refreshed at 7.81us interval.

• Automotive – automotive-grade devices are refreshed at 1.95us interval.