FPGA-ready Design Components

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Modified by Admin on Jan 23, 2014

Related Training Videos

How do I use VHDL or Verilog in an FPGA Design?

Use the following links to browse through the frequently asked questions relevant to this area of soft design. For more in-depth, visual answers to commonly posed questions, use the links to the corresponding training videos, listed on the right.

I have my own pre-synthesized EDIF models, how do i hook them into the software?
Where does Altium Designer search for presynthesized EDIF models?

I have my own pre-synthesized EDIF models, how do i hook them into the software?

User-created, pre-synthesized EDIF models can be stored in a user model folder. This folder can then be specified on the FPGA - Synthesis page of the Preferences dialog (DXP » Preferences).

User models can also be stored in a hierarchy of folders if you are developing a model for multiple target devices.

Where does Altium Designer search for presynthesized EDIF models?

The search sequence for EDIF models is:

$project_dir
$user_edif\$vendor\$family
$user_edif\$vendor
$user_edif
$system_edif\$vendor\$family
$system_edif\$vendor
$system_edif