Ethernet Protocol

The following sections take a look at the Ethernet protocol, including the format of the transmitted data frame, the interframe gap and what happens when frames of data collide during transmission.

Data Packaging Format

Data is transmitted over the Ethernet in frames. Figure 1 shows the constitution of such a frame, the fields of which are described in the sections that follow.

Figure 1. Standard IEEE802.3 Ethernet message frame format.

Preamble

This field of the frame is used for synchronization purposes and contains 7 Bytes, all of which have the bit pattern 10101010. The 7 Bytes are transmitted from left to right, with the individual bits in each byte transmitted from right to left (LSB to MSB).

The Preamble field is automatically created and inserted into the frame by the Controller, upon transmission. Upon reception of a frame from a connected PHY device, the Preamble field is stripped from the frame and discarded.

If, while transmitting the Preamble portion of a frame a collision is detected, transmission will continue until transmission of the Preamble and subsequent SFD fields are completed.

SFD

The SFD (Start of Frame Delimiter) field is used to mark the beginning of the frame. It contains a single byte with the bit pattern 10101011. The bits are transmitted from left to right (MSB to LSB).

The SFD field is automatically created and inserted into the frame by the Controller, upon transmission. Upon reception of a frame from a connected PHY device, the SFD field is stripped from the frame and discarded.

If, while transmitting the SFD portion of a frame a collision is detected, transmission will continue until the field has completed.

Destination Address

This field of the frame is used to specify the address of the PHY device to which you wish to transmit data. The field is 6 Bytes long, resulting in a 48-bit address, the least significant bit of which is used to determine whether the transmitted data is for a single, specific PHY device ('0') or for multiple PHY devices ('1').

If all 48-bits of the address are set High, then the transmission will be 'broadcast' to all connected PHY devices.

The Destination field is transmitted from right to left (LSB to MSB).
 

Source Address

This field of the frame is used to specify the address of the Controller itself (i.e. the source of the transmission). This field is also 6 Bytes in length, equating to a 48-bit address.

The Source field is transmitted from right to left (LSB to MSB).
 

Length/Type

This field of the frame can either be used to represent the length, in Bytes, of the Data field, or the frame type. The 2 Byte value in this field is translated as follows:

• If the value in the Length/Type field is less than 0600h, the value is representing the length of the data field (in Bytes). This value does not include any bytes contained in the Padding field.

• If the value in the Length/Type field is greater than or equal to 0600h, the value is representing the type of frame being sent/received.

The two bytes are transmitted from left to right with individual bit transmission from right to left (LSB to MSB).
 

Data

This field contains the main data for the frame. The Data field can be anywhere from 0 to 1500 Bytes in length and is transmitted with the least significant bit first.

Padding

This field of the frame is used to ensure that the frame is at least the minimum length required for successful Half Duplex communications using the Carrier Sense Multiple Access with Collision Detection (CSMA/CD) bus access method. This minimum frame length is 64 Bytes, not including the Preamble and SFD fields.

The length of the Padding field can vary between 0 and 46 Bytes and depends on the number of Bytes contained in the Data field:

The Padding field is automatically created with the necessary number of Bytes and inserted into the frame by the Controller, if required, upon transmission. Each padding byte inserted will have the pattern 00000000.

FCS

This field of the frame is used to provide frame checking, which is ultimately used by the receiver device to ensure that the frame has not corrupted. Frame checking is implemented using a 32-bit Cyclic Redundancy Check (CRC). The value in the field is calculated by performing a modulo 2 division of the frame content (with the exception of the Preamble and SFD fields) by the following polynomial expression:
 
G(x) = x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 + 1
 
The remainder of the division is used as the 4 Byte value for the FCS field. The most significant bit of the remainder is place as the left-most bit in the left-most byte of the field.

The FCS field is automatically created and inserted into the frame by the Controller, upon transmission. The bytes are transmitted from left to right, with individual bits transmitted also from left to right (MSB to LSB). Upon reception of a message frame, the Controller checks the CRC value. If the check reveals an error, the message is skipped. If the CRC check returns no error, the message – including CRC is loaded into the Receive Buffer. The FCS field will always be the last 6 Bytes of a received message.

Interframe Gap

The IEEE802.3 Standard specifies a minimum length of time that must be observed by a device connected to the Ethernet bus, between the end of a current frame transmission and the start of a new one. This time-slot between transmitted frames is referred to as the 'Interframe Gap'. The actual gap will depend on the mode of communications:

• When communicating at 10 Mbps, the Interframe Gap is 9.6 us

• When communicating at 100 Mbps, the Interframe Gap is 0.96 us.

Frame Deference

When configured for Half Duplex communications, the Controller constantly monitors the Ethernet bus, 'listening' for any traffic (passing frames transmitted by other devices connected to the bus). It does this using a carrier sense signal (PHY_CRS) supplied by the external PHY device. If the bus is currently busy, this signal will go High and the Controller will delay any transmission it was ready to make – that is, it defers to the passing frame already in transmission from some other device.

When the last bit of the frame currently being transmitted on the bus is sent, the carrier sense signal goes Low. At this point, the Controller starts to time the Interframe Gap. If another transmission is made by another device in the meantime, the carrier sense signal will go High again and the Controller will stop its timing of the Interframe Gap until the carrier sense signal becomes Low again.

When configured for Full Duplex communications, the Controller is not sharing the bus with any other devices – it is point-to-point connected with the PHY device. It therefore does not need to listen for traffic on the bus and hence does not use the carrier sense signal. In this mode, all it needs to do is time the Interframe Gap after completing the last bit in a current frame transmission. When the time is reached, it can transmit a subsequent frame.

Collisions

When configured in Full Duplex mode, simultaneous transmission and reception of data frames can be carried out without fear of collision, as there are only two devices connected to each other. However, when configured for Half Duplex communication and many devices are connected to the Ethernet bus, there is potential for collision of data frames – i.e. when one device starts to transmit without having detected another transmission already in progress.

With all devices connected to the bus operating normally (no faulty devices), collisions will normally only occur inside what is referred to as the 'Collision Window'. This is the window of time between a device starting to transmit a message frame and the furthest connected device on the bus detecting this transmission.

The collision window equates to the round-trip propagation time of the bus and is 64 byte times for a 10/100 Mbps configuration (corresponding to the minimum frame length of 64 Bytes).

After this 'window' there is a very low chance of collision, as all other devices on the bus should have detected the transmission and defer to it.

If a collision does occur during the collision window, the PHY device will take the collision signal (PHY_COL) High and the Controller will then continue to transmit the nibble pattern 1010 for a predefined period (3.2 us for 10 Mbps, 0.32 us for 100 Mbps) in order to ensure that the collision is propagated through the system and that the destination device(s) are aware that a collision has occurred and any received data should be discarded. This continued transmission period is known as 'Jamming'.

At the end of the jamming period, the Controller will attempt to restart transmission of that same message frame, if it detects that the bus is free.