EMAC8_MD_W - Block Diagram

Figure 1 shows a high-level block diagram for the EMAC8_MD_W component.

Figure 1. EMAC8_MD_W block diagram.

The internal structure of the Controller consists of memory-mapped registers and two distinct dual port RAM blocks, used for the Transmit and Receive message buffers respectively. In addition, two dedicated Wishbone registers are used to facilitate read/write access of these internal registers and buffers over a standard Wishbone interface.

For information on the internal registers for the EMAC8_MD_W that can be accessed from the host processor, see Accessible Internal Registers.