Winter 09 Build 8.0.0.15895 (from Build 7.1.0.14670)

PCB

• The DRC options for split planes are now correctly saved with the PCB document.
• 3D bodies that are part of a component now respect the Locked and Locked Primitive properties of the component.
• Fixed the Interactive Route Tool to not crash or hang in certain situations when the route tool was switched to 90-corner mode and in Hug and Push route mode.
• Now the interactive router will pick the net of the polygon the user clicked on when starting routing.
• Now the component clearance rule will check components that don't have any component bodies and for which the Height is set to 0.
• When a Diff Pair is pushed or shoved, the pair now maintains the defined Diff Pair gap rather than going back to a simple clearance rule.
• Fixed bug in hatched polygon pouring that was leaving big gaps around the teardrops.
• Now when starting a component drag the mouse cursor will jump to component's reference point in spite of the option that is currently set in the "Choose Component" dialog. The options in the "Choose Component" dialog will be used only when the dialog needs to pop-up.
• Enabling "Select" check-box in PCB Panel will now highlight all net objects apart from copper pours.
• The PDIF importer has been updated. Now it can be run via the "File / Import..." command from inside the PCB editor. It can no longer be run via "File / Open" command.
• The interactive route tool is now properly combining routed tracks against neighboring existing collinear tracks (the start object or terminating object) into single tracks.
• The output of polygon regions has been improved. Now they will be exported correctly if on Internal Plane layers.
• A crash that occurs when adding teardrops to a pad with an attached zero width track has been resolved.
• PCB 3D print settings will now save correctly in system locales that use a different decimal point character than '.'
• The Interactive Route Tool has an internal glossing algorithm to smooth the route and pushed tracks. An option has been added to the tool to control how aggressive the glossing is. The glossing option can be set to either Weak or Strong. Prior versions were set internally to strong, which could result in tracks being "glossed" that were not directly involved in the prior route action.
• The Toggle Units feature of all PCB dialogs have been improved. Now the toggle is working when grids are present and one of the grid cells is being edited.
• A bug whereby circles that were part of an embedded board array were handled incorrectly in the print preview and publishing a board to SmartPDF has been corrected.
• The default 3D view configurations have been updated to use the system setting for 3D model display.
• Fixed crash in Interactive Route Tool caused by keepout layer arcs.
• Fixed starved thermal DRC check for square holes.
• Now the InPolygonClass query will also work when scoping design rules like Clearance etc.
• Changed the behavior of the Interactive Route Tool for how it handles cases where the current route point is in violation. The prior behavior was an error dialog appears when interactive routing and it can't route in walk around, push, or push and hug. Message appears, "Cannot Switch route mode because the current location is in violation with a neighboring primitive. Route mode will be automatically switched to Ignore Rules." The new behavior is to temporarily switch to ignore rules mode, then automatically switch back to the prior route mode when the first mouse-click is in a non-violating area. This will allow the user the options to 1) cancel the route and fix the problem, possibly a rule, 2) Accept the violation and continue to route, 3) change widths to a smaller width to get rid of violation.
• Now when making a library from a PCB document the component's 3D bodies will keep the layers they were defined on in the PCB document.
• Fixed the interactive route tool's fanout via command ('/') to allow switching to a connected plane layer. This allows for the placement of a blind/buried via to a plane layer.
• Now the PCB ViewState will be saved inside the PCB document so the last graphical view configurations for both 2D and 3D views will be available always.
• The pin swapper will now correctly identify swappable pins in multiple placed child sheets.
• Clean All Nets now properly removes tracks stacked on top of each other.
• Fixed Interactive Route problem in Push or Hug 'N Push route modes. If the snap grid x and y were different, then no tracks could be placed.
• The DirectX display is now functioning correctly when interactive routing with the Apply Mask During Interactive Editing option turned off in Display Preferences.
• Undo now returns deleted tracks when smart track ends is enabled.
• The default checking angle for new Acute Angle rules has been changed from 90 to 60 degrees.
• Now any hidden text of type TrueTypeText or BarCodeText will no longer be output to ODB++.
• For the differential pair routing tool, as an alternative to auto-picking the second differential pair object allow the manual selection of the differential pair objects prior to invoking the tool (same as in the multi-route tool). This was added because some situations where the proximity of the differential pair objects are so close that the auto-picking of the second object can be ambigous.
• It is now possible to click and drag lines belonging to components with unlocked primitives.
• Now the "All Widths" edit-box will show 0 if the track widths per layer are different or will show the uniform value if the track widths per layer are identical. In either case the current units will be used.
• The Max/Min width rule has been improved. A new option has been added to check the physical copper as it will be manufactured, rather than individual tracks and arcs.
• Fix the interactive router to snap the mouse point to an object's center point when the mouse is moved over the object of the same net that is being routed.
• Now the slots length will be correctly exported to STEP.
• No visual indication of the state of Lookahead mode was presented to the user while using the interactive route tool, with the exception of the menu shortcuts display. Show the lookahead mode by drawing the lookahead segment as Hollow.
• Fixed false DRC starved thermals report when multiple same net split were present on the internal plane.
• Via's and Pad's are now accessible in the 3D graphical PCB view.
• A new manufacturing rule has been added to check for minimum allowed solder mask slivers.
• A new manufacturing rule has been added to check for silkscreen elements positioned over exposed copper in pads and vias.
• A new rule has been added to check for minimum clearance between silkscreen elements.
• Primitives highlighted using the Mask and Dim functions of PCB now correctly display in front of other primitives when using DirectX.
• The performance of the PCB panel when clicking on rules with either the Mask or Dim functions enabled has been significantly improved.
• The Layer Stackup Legend now writes its preferences into the registry rather than an INI files in the Windows folder.
• Improved the smoothing of traces being gathered in the multi-route tool.
• Fixed crash loading PCB Binary 3.0 (Protel 98) files.
• Now the user should be able to pick component primitives even if they are not on the current layer.
• Fixed issues with the differential pair route tool picking. The tool was sometimes finding the wrong paired object, potentially on another layer, which caused error messages.
• The "Rules" mode of the PCB Panel has been renamed to "Rules and Violations".
• Duplicate accelerator key entries in the PCB and PCB library Tools menus have been removed.
• The interactive length tuning function now correctly respects the state of the "Mask During Interactive Editing" preference.
• A spelling error in the design rule verification messages has been rectified. "Name is Dupplicate" has been changed to "Duplicate Name".
• A new manufacturing rule has been added to check the minimum clearance between pad and via holes.
• Added Interactive Route Option "Follow Mouse Trail" that allows the user to enable/disable how the route tool goes around fixed obstacles in the Push modes. In tight, small routing areas, some users requested that it would be desirable to be able to disable the "Follow The Mouse Trail" behaviour. In the Summer 08 release, the default behavior was to always "Follow The Mouse Trail". The option can be toggled during the route by pressing the '5' key.
• Picking component bodies has been improved. Now the process gives a chance to other objects that might be covered by the component body to be selected. An object pick list will pop-up always when more then one object could potentially be selected.
• The visibility of embedded board arrays is no longer dependent on the layer that was active at the time they were placed. Visibility can now be controlled via the view configuration.
• German and other regions that use a comma as the decimal point will now be able to save 3D print outjob configurations correctly.
• Vias were being pushed off-grid with the interactive route tool and the origin set.
• A new manufacturing rule has been added to check for and locate any net antennas in the design.
• Now the DRC report file will be created in the Output directory set for the project the PCB document is in. This directory can be found in the Project dialog / Options tab.
• Added four new auto generated component classes for Top Side, Bottom Side, Inside and Outside Board.
• Now the user can run individual or sets of rules and rule classes directly from the PCB Panel using the Right Click Menu. The same options are also available for clearing any violations.
• A crash when 'R' is pressed in the Show/Hide tab in the view configuration dialog has been fixed.
• Via and pad holes will now be the correct size in 3D.
• The 'Configure Pin Swapping For Component' dialog no longer loses the pair swap that is entered.
• The "standard" ODB++ font file is now correctly exported as "standard" rather than "Standard".
• Fixed the interactive route tool commands of fanout via ('/') key and the add via with no layer change ('2') to honor the lookahead route mode.
• Now the Bottom Side non-orthogonally rotated extruded bodies will be exported to STEP with the correct rotation.
• Drag operations in PCB now correctly adhere to the mask during interactive editing preferences.
• The create board outline from model command has been improved. It is now possible to align the model with the plane of the PCB board definition.
• The default settings for the visible grid have been changed such that they are multiples of the current snap grid.
• It is now possible to ignore (as well as hide) parts of a mechanical assembly for DRC.
• Fixed a crash in the Interactive Routing tool that was caused by a bug in the via pushing algorithm.
• An issue with the 'Boardoutline from 3D Model' command whereby cutouts were created with incorrect outlines has been resolved.
• The logo creator script has been improved so it is more tolerant of non-monochrome images, non-white pixels now become tracks on the PCB. An issue with the Mirror X options was also fixed.
• Fixed the interactive route tool elbowing after a mouse click to be more consistent.
• Net names on electrical objects are now correctly updated after performing ECO operation.
• Added 'Zoom Selected' operation to popup menu in PCB panel allowing easier navigation.
• The sensitivity of the PCB navigation zoom now matches schematic.
• The Component Clearance rule was crashing when applied to a 3D model that had all its Parts disabled for DRC checking.
• Status messages during DRC run now include the details about the rule being checked.
• A status message and progress bar are now presented when building a DirectX scene.
• Fixed crash in 'Legacy Hole Size Editor'. In this release this legacy tool is moved under 'Legacy tools' menu with other legacy tools. It is highly recommended to use 'Hole Size Editor' mode in PCB panel that gives more flexibility and control over hole review and editing.
• Dimming and masking now both work in 3D and highlighted objects are drawn on top.
• 3D bodies containing pins that protrude through holes now draw correctly.
• 3D body identifiers are now more descriptive in the status bar, PCB panel and ambiguous selection dialog.
• 3D bodies which are made invisible due to the STEP/Simple preference are no longer selectable.
• The "Gerber Setup" and "NC Drill Setup" dialogs now default to the 2:5 format in Imperial units and the 4:4 format in Metric units.
• The accuracy of the acute angle rule has been improved. This rule now checks the physical copper as it will be manufactured rather than analyzing track pairs.
• Now the Reference Point of the Move Selection command will be maintained even if locked primitives are present in selection.
• Now the user will be able to drag and drop components from the PCB Panel onto the PCB Window similar with the drag and drop from the Library Panel. The components can be rotated, flipped and their properties changed.
• No solder mask sliver violation will be created if the solder mask openings of two objects are touching or overlapping.
• Now the Net Antenna check will no longer create violations for tracks, arcs etc. that are directly routed into polygon pours.
• Now the Net Antenna violations will display the layer on which the violation occurred.
• The fanout command now works correctly so that the escape routes are now placed correctly on the mid layers.
• A crash that occurs when pin swapping is enabled in the interactive router has been rectified.
• The 'Configure Swapping Information In Components' dialog now displays the physical designators rather than the logical designators.
• PCB documents imported from P-CAD will no longer crash if they contain copper pour polygons with more than 5000 vertices.

Schematic

• After part swapping in the PCB editor the generated ECO no longer incorrectly moves pins between component subparts.
• The Place Sheet Entries Automatically feature now works correctly when wiring from a bus pin on a component to a sheet symbol.
• Predefined harness connectors can now be placed based on the harness type of sheet entries, ports, harness entries and signal harnesses. After right clicking on schematic objects with a harness type, the following command appears in the menu: "Place Harness Connector of Type [Name]".
• There is a new Special String available in the Schematic Editor, =versionControl_RevNumber. This string will display the Version Control Revision Number and is applicable to Schematic Sheets and components (when added as a parameter to that component).
• A memory leak involving compilation of projects with lots of buses has been fixed.
• Newly drawn schematic primitives that don't match the "Display only ..." filter no longer appear in the SCH List panel.
• The Place Predefined Harness Connector dialog has an additional option which controls whether the harness entries should be sorted, or the order in which the harness entries appear in the harness definition should be preserved. The harness definitions generated from placed harness connectors by the system are no longer sorted by name, but their graphical position.

FPGA

• Port Name and Direction information in the Live Update Panel are now correctly populated while targeting a Xilinx CoolRunner or CoolRunner2 CPLD device.
• A new option (EDIF Files) has been added to the Zip File Options page of the Project Packager to include pre-synthesized cores to the generated zip file.
• Map Design stage of the FPGA flow no longer failed with an error "Ignored duplicate entity "TimingController" in file I2S_W.VQM. Used entity in file WB_SHARED_SDRAM.vqm" while targeting an Altera device and both the I2S_W and WB_SHARED_SDRAM cores are used.
• Compiling an un-saved FPGA or Core project is now prompting to save all design files and is no longer causing an exception to occur.
• A new option was added to C Code Symbols to automatically register outputs once the function has completed execution.
• A new option was added to C Code Symbols to allow the top level function to begin execution upon rising edge of the Start signal, rather than a high Start signal.
• Support for Aldec Active-HDL from version 7.2 to 8.1 have been added.
• Dual port memories with a width no equal to 8 are now properly initialized when generated from a global enum type variable used in a C code symbol.
• Sheet Symbol Entries are now properly generated while using Generic values in VHDL files.
• The document AP0102 Linking an FPGA Project to a PCB Project.pdf has been updated in line with the current software functionality.
• A new violation type was added to project options: "HDL Identifier Renamed", in the category "Violations Associated with Documents". This controls the error reporting level when the VHDL and Verilog netlisters are required to change an identifier (for example, to replace invalid characters).
• Variables of type array are no longer display in one line only in the Watches panel and it is now possible to visualize array of complex variables such as structures.
• The document TR0176 Custom Instrument Reference.pdf has been updated with respect to images of the Custom Instrument Configuration dialog.
• Using the __nop() function while targeting a MicroBlaze processor is no longer causing an error - unresolved external: ___nop;
• The NB2DSK01 firmware has been updated and a display problem after pressing the Home button and ejecting the SD-Card no longer occur on the TFT.
• The JTAG Viewer Panel button in the Instrument Rack panel has been hidden for the NXP LPC 2000 devices to avoid opening an empty Live Update panel.
• Signal harnesses can now be used in FPGA and Core projects.
• The Configure dialog of the Digital IO component has been reviewed and is no longer accepting signals wider than 32 bits for the Slider and Bar controls.
• The TInstrumentLed button available for the Custom Instrument component has been revised and is now properly operating and displaying its glyph.
• The Actions and ActionCount properties of the TActionList component available for the Custom Instrument can now be used at design-time.
• Design-time editors for the TActionList, TImageList and TPopupMenu have been added in the Configuration dialog of the Custom Instrument.
• Context-sensitive 'F1' help has been included for the C Code Symbol and C Code Entry primitive objects. Hover over or select one of these objects and press F1 to load corresponding help information into the upper region of the Knowledge Center panel.
• Instrument Panel for the Digital IO component is now properly updated after the signals have been modified and the FPGA project has been re-build.
• The Embedded Intelligence documentation areas (nav pages) of the Knowledge Center panel and Altium Designer have been updated to reflect new training center videos that have become available.
• The Nexus JTAG chain is now automatically configured when using soft components - it is no longer required to add the Nexus JTAG connector on the top sheet for FPGA projects.
• IO Standard, Slew Rate and Drive Strength constraints are now properly passed to Lattice ipsLEVER.
• A new Export Data right mouse click command has been added in the Logic Analyzer Panel to allow data to be exported to a file.
• Support for NXP LPC24XX discrete processors has been added in the devices flow.
• What's This Help (?) level information has been added for the Custom Instrument Configuration dialog.
• EMAC32 core has been revised and its access is no longer breaking half way through while connected to a WB-multimaster component.
• The progress bar shown when generating HDL for C code symbols now does not appear.
• A new Application Note has been added - AP0166 Testing and Debugging Your Embedded Intelligence.pdf. This document takes a look at the range of tools available to aide in the debugging of your embedded intelligence - the FPGA design itself and any embedded program code required by processors within that design.
• The document TU0135 Adding Custom Instrumentation to an FPGA Design.pdf has been updated. This latest version contains updated images relating to the Custom Instrument Configuration dialog, as well as enhanced information for the section 'Hooking the Script up to the GUI'.
• Performing a sector blank check operation is no longer failing on NXP LPC2000 devices.
• Options for Embedded Projects have been reviewed to default the toolchain to TASKING 3000 and the output directory to "Output".
• FPGA project synchronization is now possible while using custom board level implementation component symbol by linking the Design Item ID to a NexusDeviceId parameter.
• Synthesis stage of the FPGA flow now properly stopped when a "Port xxxx will be automatically assigned to a Device Pin" error is found.
• Internal flash memory architecture in the Options dialog for Embedded project is now properly setup for NXP the LPC2109, LPC2119 and LPC2129 discrete processors.
• The JPEG decoder core (WB_JPEG_V2) has been optimized and its unused select line has been removed.
• IO buffer symbols with specific differential pair standards (including OBUFDS_BLVDS_25, ...) are no longer missing in the Spartan-3 FPGA integrated library.
• The NB2DSK01 firmware has been updated and is now showing an new Boot From Device option in the Boot page to allow Spartan-3AN devices to be configured with their integrated In System Flash device.
• When documents are arranged in vertical split view, the Devices View is now properly resized after dragging it into a wider view.
• Units options for OpenBus documents have been disabled to avoid inconsistent size conversion of OpenBus objects.
• The Synthesis stage of the FPGA flow no longer stop with an error "expression has XX elements ; expected 20" while the design includes a WB_BOOTLOADER component.
• The NB2DSK01 firmware has been updated and the RTC system is no longer taking time of the SPI bus interrupting the use of the SPI bus for the Daughter Board and Peripheral Boards.
• Default device for the Browse Physical Device dialog has been updated to a Spartan-3 device.
• An error "SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION" no longer appears when trying to program the internal flash of NXP LPC2129 devices with a file size bigger than 4096 bytes.
• Control C code entries (such as Start, Done and Reset) cannot be moved to another C code symbol via Ctrl+Drag since they are related to the configuration of the C code symbol and should not be edited or deleted.
• OpenBus system documents now have signal harness interfaces. The sheet symbol for the OpenBus system document will have harness typed sheet entries representing groups of pins. The sheet entries will also be grouped by component. Harness connectors can be used to connect the sheet entries to the port plugin components.
• Synplify no longer fail to generate edif files for Xilinx Spartan-3L devices.
• FPGA Generic pre-compiled component models have been added it is now possible to simulate the VHDL simulation examples using Aldec Active-HDL 6.1, 7.2, 7.3 and 8.1.
• Adding 1-bit width signals to the Digital IO component is no longer causing the Synthesis stage to fail with an error "type error near xxx ; expected type std_logic_vector ".
• It is no longer possible to add a TSK3000 processor into the JTAG chain for physical devices in the Devices View.
• The warning "WARNING - par: Placement timing preferences are hard to meet. However, placement will continue. Use static timing analysis to identify, errors." is no longer treated as an error and causing the Place and Route stage of the FPGA flow to fail while targeting a Lattice device and using ipsLEVER 7.1.
• A new configurable GATE component has been added to the FPGA Configurable Generic library to place AND, NAND, OR, NOR, XOR and XNOR with the option to perform bitwise operations on bus inputs or to apply registered outputs.
• Constraints from Altium Designer constraint files (including timing constraints, ...) are no longer overwritten and not passed to the vendor tools while using the Synplify synthesizer.
• A new configurable BUS_JS component has been added to the FPGA Configurable Generic library to place bus joiner and splitter with the option to set the bus width.
• Unsupported Sharp Bluestreak LH7A404 devices have been removed from the Browse Physical Devices dialog.
• Translate Design stage of the FPGA flow is no longer failing with an error "logical block 'U1/M2_EMAC' with type 'Memory_M2_EMAC' is un-expanded" when using the EMAC8_W component and targeting a Lattice XP2 device.
• A new configurable component has been added to the FPGA Configurable Generic library to place Inverter and Buffer with the option to set the bus width.
• Build stage of the FPGA flow is no longer failing with an error "ANOM:003 Many top level design" while using the WB_MEM_CTRL SDRAM controller and targeting an Actel device.
• The Synthesis stage of the FPGA flow is no longer failing with an error "Error executing Synplicity VHDL/Verilog HDL Synthesizer with code 2" while using Synplify for Lattice available in ispLEVER 7.1 SP1.
• C Code Symbols now have a list of additional files. Only these files along with the source file containing the top level exported function will be compiled. Previously, all project documents were passed to the C to Hardware Compiler.
• To prevent problems, It is no longer possible to edit the Name of Component and the Location of Port and Links in OpenBus document through the OpenBus Inspector Panel.
• Xilinx XCF devices no longer require to be programmed twice in a row to be successfully configured.
• OpenBus files are now stored in new format (v. 6.0), with components' pictures embedded within. This change will prevent older versions of AD from opening OpenBus files created in latest AD.
• Xilinx XCF16P and XCF32P devices can now be properly reset.
• A new configurable REGISTER component has been added to the FPGA Configurable Generic library to place D Flip-Flop and Transparent Latch with the option to apply Synchronous or Asynchronous Set and Reset.
• A new configurable MEMORY component has been added to the FPGA Configurable Generic Library. The memory component supports ROM and RAM memory types with single or dual port interface. Clock polarity can be set to rising edge or falling edge. Data width and memory depth are fully configurable as well as optional byte write and enable controls. Vendor specific distributed memory resources can be utilized as one of options for this flexible component. Both RAM and ROM content can be initialized from file.
• A new configurable component has been added to the FPGA Generic Simple Library. The FIFO component supports same clock on both read and write ports configuration as well as truly independent clock mode. Vendor specific distributed memory or Block RAM resources are selectable from the configuration dialog. Optional status ports with empty and full flags as well as data count on read port and number of words that can be written to the write port are supported. Clock option can be set to rising edge or falling edge. Optional almost empty and almost full flags have configurable thresholds.
• All configurator dialogs of OpenBus components have additional fields to modify the Designator and Interface Type of the component, and a button which invokes the OpenBus Signal Manager. Non-configurable components have a new dialog which contains these fields.
• A new SD Card Controller peripheral component and OpenBus component was added to enable communication between a host processor and s SD Card device.
• The DSF drivers and options have been removed and are now replaced by the new Software Platform system.
• Compile stage for embedded projects in the Devices View is strongly indicating a failure (red button) while it passed successfully for some projects.
• When a harness connector is hovered over a port plugin component (which is underneath the cursor), pressing the Insert key will cause the spacing between the harness entries to copy the spacing between the pins of the component.
• Configurable component MEM_CTRL has been improved. Parallel_FLASH timing options allow delays to be greater than 10 clock cycles.
• Editing of an OpenBus component designator via the "Parameter Properties" dialog (accessed via double clicking on the designator) will now automatically update the processor's peripheral and memory devices. Undo/redo of changes to component designators and configuration will also automatically update the processor's peripheral and memory devices.
• Custom Instrument controls have been review for consistency and cosmetic purpose. This includes new display options.
• The Custom Instrument no longer fails to synthesize while using third party synthesizer like XST and Synplify.
• The NB2DSK01 firmware has been updated and power cycling the NB2 while Windows XP is running on some machine is no longer causing a Windows system crash.
• It is now possible to generate Xilinx configuration files for non Xilinx PROM devices.
• FPGA Hardware examples have been updated with configurable Digital IO instrument.
• The Custom Instrument now has the option to export a Wishbone interface. A Custom Instrument OpenBus Component was added, allowing it to be placed in an OpenBus document. Instrumentation services are also available in the Software Platform.
• The Choose Vendor Constraint File Type dialog is no longer showing UCF files as Lattice vendor constraints files.
• It is now possible to add Lattice LPF constraints files to an FPGA project.

System-level

• A problem where changing print options during print preview causes the wrong document to be displayed has been fixed.
• The ECO manager has been improved. The location of the ECO logs can now be controlled through the project options dialog.
• In the past when a document is detected as modified in disk, Altium Designer only pops up document modification warning. Now, the user has an option to reload the document.
• Startup screen doesn't block visibility of other applications' windows under it.
• The version control status of newly created files and projects now refreshes correctly.
• The Storage Manager panel now has a combined view of backups, version control revisions, and releases in a single timeline.
• Parts placed from DBLibs with multiple key lookup no longer have blank Design Item IDs.
• Importing certain P-Cad PCB files would cause an exception resulting in the design not loading. This was tied to copper pours. This has been fixed.
• PADS through-hole pads with nonzero dimensions on only one layer are now imported correctly.
• Numerical parameters in the Bill of Materials are now exported to Excel as numbers, not strings.
• Publish To PDF of a Bill of Materials from a particular SchDoc or PcbDoc file now works correctly.
• The folder for saving Altium Web Updates can now be user-defined in Preferences. The "Updates will be downloaded to" field is now editable and a browse icon is added.
• Running Publish To PDF scripts no longer modifies PDF Setup.
• During import of Allegro Design files, Package Keepouts were all being translated to the Top layer instead of their prospective layers. This has been corrected.
• You can now generate DRC Reports from the Output Job Editor
• The standard units ADODB, DB, DBActns, DBClient, DBCommon, DBCtrls, Math, MidasCon, ObjBrkr, Provider, and SConnect which were missing from Altium Designer 6.8 have been restored to the DelphiScript language.
• You can now generate ERC Reports from the Output Job Editor
• Reporting of errors from Subversion during Add To Version Control has been improved.
• The paths of svn.exe and svnadmin.exe now stick in the Preferences if changed after setting up Version Control.
• A new Script Output type has been added which allows generation of outputs and configuration from the OutJob document in any user-defined format.
• Problems in harness definitions can be viewed using the Harness Definition Problem Finder. This can be accessed from the menu item Tools > Harness Definition Problem Finder.

Embedded

• Naming a variable "help" is no longer returning the value "No such help topic" in the Watches, Evaluate and Debug Console panels.
• The Step Into, Step Over, Step Into Instruction and Step Over Instruction commands in the Debug toolbar for c code documents are no longer greyed out during simulation and debugging sessions while trying to access some system functions.
• A message "Press ESC to Abort" no longer appears in the Status Bar while downloading hex code to a processor memory.
• The debugger no longer fail to start when multiple soft components (instruments, processors, ...) are in the JTAG chain.

Signal Integrity and Simulation

• A problem simulating P-CAD netlists that contain multipart components with a colon character in the designator has been fixed.
• The way that model parameters are stored has been changed internally so that the values of parameters defined as equations will now change correctly as a global parameter is swept.
• Comments are now supported in Piece-wise Linear source files. Both * (whole line) and ; (in-line) comments are supported.
• Support for the PSpice .FUNC command has been added. This allows definition of custom functions that can be used in other numerical expressions.
• The DC Sweep Analysis has been improved. The Circuit Temperature is now avilable to be swept so that a plot of voltage/current on the y-axis and Temperature on the x-axis can be obtained.
• Support for PSpice DDT(x) function has been added. This takes the time derivative of x (during Transient analysis only).

Library Management

• The currently selected pins are now kept in sync between the schematic library editor, the SCH Library panel, and the model preview frame.
• Updating from libraries (using Full Replacement of parts) now includes parameters' graphical attributes like font and colour.
• Integrated Libraries are no longer locked when installed, allowing them to be overwritten by other users or by version control updates.
• Fonts and colours of component designators and comments now appear correctly when placed from libraries.
• Autopositioning of parameters is now applied correctly when components are placed from libraries.

CAM Editor

• CAMtastic®'s ODB++ loader has been improved. Now ODB++ databases containing certain rotated custom symbols will be corectly loaded.