Signals with no Load

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Modified by Jason Howie on Feb 26, 2014

This compiler hint appears when a pin (with I/O Type Output or IO) or a sheet entry (with I/O Type Output orBidirectional) is not connected to another part of the circuit (e.g. pin, port, sheet entry, power port, offsheet connector). The message is displayed in the Messages panel in the following format:

Signal SignalName has no load,

where

SignalName is the name of the affected signal.

Default Report Mode

Warning

Recommendation

If the offending pin or sheet entry is intended to be used within the design, ensure that it is connected to the relevant point in the circuit.

If the offending object is a component pin and you do not intend to use it within the design, simply place a No ERC directive on the pin.

If the offending object is a sheet entry that you do not intend to use, simply remove it from its parent sheet symbol.

Notes

This violation type will only be displayed when compiling an FPGA project (*.PrjFpg), a single source schematic that is part of an FPGA project, or a free schematic document.