VHDL Generation Settings

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Modified by Admin on Nov 6, 2013

The VHDL Generation Settings Dialog.

Summary

The VHDL Generation Settings dialog offers options for generating one or more VHDL documents from the source schematic sheet(s).

Access

In Schematic Editor, run command Design » Netlist For Document » VHDL File and Design » Netlist For Project » VHDL File.
In Netlist Outputs section of an Outjob file, right click an existing VHDL file (create a new one if there is none), then choose Configure to access this dialog.

Options/Controls

Generate mutiple VHDL files - When the source is the entire project, this option determines whether separate VHDL files (*.vhd) will be produced for each source schematic sheet in the project (option enabled), or whether a single VHDL file will be generated (option disabled). In the former case, each VHDL file will be given the name of its source schematic sheet. In the latter case, the single VHDL file will be given the name of the project.
Convert parameters as attributes - This option, when enabled, will take all parameter definitions associated with objects on the source schematic(s) and convert them to attribute declarations in the generated VHDL file(s).
Insert crossprobe strings - This option, when enabled, causes the insertion of comments in the VHDL file, referencing which part of a source schematic the corresponding VHDL code entry was generated from.

Notes

VHDL output can be generated in one of two ways:

When using an appropriately configured output generator defined in an Output Job Configuration file (*.OutJob), Output will be generated upon running the configured output generator
When directly from within an active schematic document using the Design » Netlist For Document » VHDL File and Design » Netlist For Project » VHDL File menu commands, for single document or project-level netlisting respectively, Output will be generated immediately upon clicking OK in the VHDL Generation Settings dialog.

The settings defined in the VHDL Generation Settings dialog when generating output directly from the schematic are distinct and separate to those defined for the same output type in an Output Job Configuration file. In the case of the former, the settings are stored in the project file, whereas for the latter they are stored in the Output Job Configuration file.

The output path for generated files is set in the Options tab of the Options for Project dialog. By default, the output path is set to a sub-folder under the folder that contains the Project file and has the name: Project Outputs for ProjectName. The output path can be changed as required. If the option to use a separate folder for each output type has been enabled in the Options tab, then the VHDL file will be written to a further sub-folder, named: VHDL Output.

When generated, the output will be added to the project and appear in the Projects panel under the Generated folder, in an appropriately-named sub-folder. If you have used a separate folder for each output type, then corresponding (separate) Generated folders will be added to theProjects panel (e.g. Generated (VHDL Output)).