FPGA Signal Manager

Parent page: WorkspaceManager Dialogs

Summary

This dialog allows the designer to configure I/O standards, slew rates and drive strengths for each pin of an FPGA device.

Access

In FPGA project, run command Tools >> FPGA Signal Manager to access this dialog.

Options/Controls

• Pin Details Grids - This table contains a list of signals for the FPGA project. Click on a signal name and then the IO standard before you can define the slew rate and the drive strength characteristics for this signal. The list of IO standards are only applicable for that particular FPGA will be available.

You can drag a column header into the dark area of the dialog to group by that column for easier reference.

The FPGA Signal Manager dialog lists all the pins for the device. The following information columns can be displayed:

• • Signal Name*
  • I/O Standard*
  • Slew Rate*
  • Drive Strength*
  • Electrical Type
  • Pin Number
  • I/O Bank Number
  • Whether or not the pin is an IO Pin
  • Whether or not the pin is an VREF Pin
  • Whether or not the pin is an CLK Pin
  • Whether or not the pin is an Config Pin

Columns marked with an asterisk (*) above are displayed by default. To toggle the visibility of a column, simply right-click inside the main grid of the dialog and enable/disable the column from the Show/Hide Columns sub-menu as required.

The only editable fields for each pin are those for IO Standard, Slew Rate and Drive Strength. These fields are context sensitive - the list of available I/O Standards will be those applicable to the target FPGA device and the list of entries for Slew Rate and Drive Strength will depend on the particular I/O Standard chosen. You cannot type directly into these fields.

Click on a field to access a drop-down of possible entries from which to choose or, alternatively, right-click anywhere within the row for a signal and select an available I/O Standard, Slew Rate and Drive Strength from the subsequent sub-menus.

• Assign Unconstrained Signals - Click to assign any signals within the design that have not been assigned to a physical pin of the FPGA device. If all signals are already assigned to pins, after clicking on this button a warning dialog appears.

Notes

Signal electrical characteristics are stored in a constraint file and not in the PCB document or project. An FPGA project must therefore be linked to the PCB project and the relevant signal characteristics stored in a constraint file therein.

If you are working within a PCB project - either on the schematic sheet for the FPGA component or the PCB document itself - and you try to launch the FPGA Signal Manager dialog, the No Linked FPGA Project dialog will appear. The dialog gives you the option of browsing for an existing FPGA project with which to link the PCB project to, or to create a new one. If you choose to create a new FPGA project, the PCB TO FPGA Project Wizard will appear.

Clicking on the header for a column will toggle the sorting of the information between ascending and descending order. All columns will be affected, but the rows will be sorted according to the information column whose header you click on.

You can choose to group pins together by one or more specific columns of information. To do this, simply click, drag and drop the header of the desired information column into the region immediately above the headers.

Column order can be changed by clicking and dragging the header for the column left or right until vertical green arrows appear. These arrows show the point of insertion.

FPGA devices generally support a range of I/O standards. These standards follow industry specifications and often include options like LVTTL, LVCMOS and PCI to name a few. This enables the FPGA to communicate directly with other devices requiring a certain standard. Often the standards will also support further customization including the slew rate, current strength and voltage.

Each device will have its own set of supported standards. Only supported standards can be selected for the current device.

There is a complex set of interactions between different I/O standards in an FPGA. Some I/O standards will be able to co-exist while others are mutually exclusive. Often the requirements are limited to I/O banks, such that all pins within an I/O bank on an FPGA must have compatible I/O standards. This becomes particularly important with voltage referenced standards such as GTL, as an I/O bank will generally only be able to support one voltage reference value.

The interaction of selected I/O standards with one another is not modeled here and vendor documentation should be referred to for more detailed information. As a general rule of thumb, keeping pins using different I/O standards in separate I/O banks will ensure compatibility. Any errors will be picked up when the design is processed by the Vendor Place & Route tools.