Hole To Hole Clearance

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Modified by Admin on Feb 27, 2014

Rule classification: Binary

Summary

This design rule ensures checking of manufacturing compatibility of drilled holes. When enabled, it will flag any multiple vias / pads at the same location or overlapping pad / via holes. There is also a flag to allow stacked microvias or not.

To summarize, this rule:

Flags any multiple vias / pads at the same location;
Flags any overlapping pad / via holes;
Flags or not any stacked micro-vias.

Constraints

Allow Stacked Micro Vias - Check this option to allow Micro Vias to be stacked.

There are many advantages of microvia: it requires a much smaller pad, which saves the board size and weight; with microvia, more chips can be placed in less space or a smaller PCB, which results in a low cost; and with microvia, electrical performance improves due to a shorter pathway.

Hole To Hole Clearance - Set a clearance constraint between holes, the default vaule is 0.254mm.

How Duplicate Rule Contentions are Resolved

All rules are resolved by the priority setting. The system goes through the rules from highest to lowest priority and picks the first one whose scope expression(s) match the object(s) being checked.

Rule Application

Online DRC and Batch DRC.