Verilog Netlist Output Options

Verilog output options are set up in the Verilog Generation Settings dialog.

Content and Use

The Verilog Generation Settings dialog offers the following options when generating one or more Verilog documents from the source schematic sheet(s):

• Generate modules for blackboxes
  - If you enable this option, at the end of the output file (the generated Verilog netlist) the empty modules for these components from the schematic will be declared. When you go to synthesis stage in Altium Designer, the synthesiser will look at your black boxes and how they are wired but it needs information about port sizes etc. Verilog as a language, doesn't tell you this during component instantiation. In VHDL, before you instantiate a blackbox, you have to declare it and that includes port direction and size for each pin. Verilog is a bit more flexible, it needs a black box name and it doesn't care about port size or its direction. Simply you don't have enough information to properly synthesise this code. Thus we have to "declare" modules so the synthesiser will know each port size and direction for the modules.
• If you disable this option, these modules are not declared and it's up to the user to provide full source code for each black box for synthesis. By default it is enabled.
• Generate multiple Verilog files
  - when the source is the entire project, this option determines whether separate Verilog files (*.V) will be produced for each source schematic sheet in the project (option enabled), or whether a single Verilog file will be generated (option disabled). In the former case, each Verilog file will be given the name of its source schematic sheet. In the latter case, the single Verilog file will be given the name of the project.
• Convert parameters as attributes
  - this option, when enabled, will take all parameter definitions associated with objects on the source schematic(s) and convert them to attribute declarations in the generated Verilog file(s). By default it is enabled.
• Insert crossprobe strings
  - this option, when enabled, causes the insertion of comments in the Verilog file, referencing which part of a source schematic the corresponding Verilog code entry was generated from.

Notes

Verilog output can be generated in one of two ways:

1. using an appropriately configured output generator defined in an Output Job Configuration file (*.OutJob). Output will be generated upon running the configured output generator
2. directly from within an active schematic document using the *Design » Netlist For Document »* Verilog File and *Design » Netlist For Project »* Verilog File menu commands, for single document or project-level netlisting respectively. Output will be generated immediately upon clicking OK in the Verilog Generation Settings dialog.

Note : The settings defined in the Verilog Generation Settings dialog when generating output directly from the schematic are distinct and separate to those defined for the same output type in an Output Job Configuration file. In the case of the former, the settings are stored in the project file, whereas for the latter they are stored in the Output Job Configuration file.

The output path for generated files is set in the Options tab of the Options for Project dialog. By default, the output path is set to a sub-folder under the folder that contains the Project file and has the name: Project Outputs for ProjectName. The output path can be changed as required. If the option to use a separate folder for each output type has been enabled in the Options tab, then the Verilog file will be written to a further sub-folder, named: Verilog Output.

When generated, the output will be added to the project and appear in the Projects panel under the Generated folder, in an appropriately-named sub-folder. If you have used a separate folder for each output type, then corresponding (separate) Generated folders will be added to the Projects panel (e.g. Generated (Verilog Output)).