Validation Output Reports

Altium Designer provides the ability to define and run validation reports as part of an Output Job file. You can setup and run a Differences Report (using the comparator to determine if the source and PCB design documents are correctly in-sync), an Electrical Rules Check (checking the electrical/drafting validity of the captured source design), a Design Rules Check (checking the validity of the PCB document in relation to specified board-level design constraints), and a Footprint Comparison Report (which compares footprints on the board against their source library to ensure they are up-to-date, and matched).

You can run and generate reports 'standalone', directly from an Output Job file, or as an integral part of Altium Designer's high-integrity Board Design Release Process. However you use them, these reports provide that extra level of validation, giving additional peace of mind and ensuring the integrity of your design data.

Adding and Defining the Reports

The four validation reports are available from the Validation Outputs section of an Output Job file. To add a report, simply click the [Add New Validation Output] button and choose the required report from the menu.

Example validation reports defined in an Output Job file.

Configuring a Differences Report

Configuration of a Differences Report is performed from the Differences Setup dialog – accessed by double-clicking on the report entry. Simply define, for each comparison type, whether differences are to be detected (Find Differences) or ignored (Ignore Differences) when running the validation.

Example configuration for a Differences Report.

You can configure a Differences Report to be stricter or more lenient than the settings defined in the Project Options for your project – it's up to you. At any time, you can reset the settings of your Differences Report to the same as your Project Options by pressing the Set To Project Default button.

Configuring an Electrical Rules Check (ERC)

Configuration of an Electrical Rules Check is performed from the Electrical Rules Check Setup dialog – accessed by double-clicking on the report entry.

Example configuration for an Electrical Rules Check.

The dialog provides familiar Error Reporting and Connection Matrix tabs to actually define the error reporting as required. In addition, the Columns tab provides two key areas:

• Validation – here, you can specify a maximum tolerated error level when using the ERC output generator as part of validation during the board design release process. The validation stage of the release process flow (in either Design or Release modes) uses the checking defined in the Output Job only, and not the project-level ERC checking. In this way, you can define an even more restrictive/rigid set of checks to be passed, in turn ensuring even higher integrity of the design data.

• Preview – shows the current errors detected for the design, based on validation using the error checking defined on the tabs within the dialog. Change a checking level and the design is re-validated (recompiled) dynamically, and the preview region updated. Use the options in the Show Columns region of this tab to toggle display of the corresponding columns within the preview area.

Your Electrical Rules Check Report can be stricter or more lenient than the settings defined in the Project Options for your project. You can reset the settings of your Electrical Rules Check Report to the same as your Project Options by pressing the Set To Project Default button.

Configuring a Design Rules Check (DRC)

There is no separate configuration dialog for a Design Rules Check validation report. The checking is performed using the settings defined for the PCB document in the Design Rule Checker dialog.

Footprint Comparison Report

The Footprint Comparison Report compares each footprint on the PCB design to the source component in the library it came from. If the source cannot be found for a footprint it will be marked as un-matched. For components which are matched, a graphical comparison is executed to ensure that the current footprint on the PCB is completely up to date and there are no changes in the library which would affect the implementation of the part on the PCB. To save computation time, the Footprint Comparison Report can be configured to graphically compare the footprint on the board with the library source only on the layers selected by the user in the Update From PCB Libraries - Options dialog.

Example configuration for a Footprint Comparison Report

Design Release Validation

Related articles: Design Data Management System - old

Using validation reports defined in an assigned Output Job file, Altium Designer provides the ability to validate your designs as an integral part of its board design release process. These validation checks will be performed on every release, and the release will fail if any validation checks are not passed successfully. This gives you additional peace of mind that costly errors do not creep in to your released designs due to last minute changes.

Validation is run at the Validate Design stage of the process flow within the PCB Release view. In Design Mode, the validation checks are performed directly on your project, before outputs are generated. In Release Mode, the release flow first builds a self-contained snapshot from your project that includes all project documents and external dependencies, and the validation checks are performed on this snapshot. This provides additional security that the snapshot has correctly captured all the required dependencies for your project.

Example of a successful validation stage being run with the PCB Release view configured in Design Mode.