Release notes for Altium Designer 10 update (10.700.22943)
Additional Resources
Updated plug-ins from release 10.651.22821 to 10.700.22943
Date: 10 October 2011
System Components: Altium Designer Base
4530 | No ERC Directives in schematic have been enhanced and can now suppress specific violations. Only the selected warning or error conditions are suppressed and any other warning or error will be detected and reported. View BugCrunch report #152. |
4978 | Added the options to include all notes, exclude collapsed notes, or exclude all notes from print and PDF outputs. View BugCrunch report #459. |
4998 | An issue whereby a Japanese text field was truncated in the Bill of Materials report has been resolved. View BugCrunch report #472. |
5347 | An issue with saving and loading localization preferences has been fixed. View BugCrunch report #822. |
5406 | The "Update from PCB library" command now shows differences between pad holes. View BugCrunch report #874. |
System Components: Altium Designer Support
4961 | An issue where by a Protel 99SE ddb file saved in a Non English version Windows XP would crash on load has been resolved. |
System Components: PCB System
4856 | The board insight display panel now redraws the preview panel to match the primitives as they are added to the panel on hover. View BugCrunch report #322. |
5000 | An issue has been resolved whereby PcbDoc files containing dimensions would crash when opened on Windows XP Japanese |
5353 | Fixed problem with very large polygon pour thermal spokes potentially causing clearance violations. View BugCrunch report #853. |
5386 | An issue has been resolved whereby PCB Binary 4.0 Files containing Coordinate Objects would crash on loading. The error was identified where an intermediate PCB Binary 4.0 file was generated during the process of importing a 99SE file. View BugCrunch report #859. |
5406 | The "Update from PCB library" command now shows differences between pad holes. View BugCrunch report #874. |
5410 | Net on shelved polygon is now correctly updated when updated from Schematic document. View BugCrunch report #612. |
5411 | PCB DRC now issues warning if document contains shelved polygons. View BugCrunch report #666. |
System Components: PCB Support
5412 | Following the use of the IPC® Compliant Footprint Wizard, some operations on the PCB library document caused unstable conditions unless the library was closed and re-opened. This has been resolved. View BugCrunch report #869. |
System Components: Schematic System
4530 | No ERC Directives in schematic have been enhanced and can now suppress specific violations. Only the selected warning or error conditions are suppressed and any other warning or error will be detected and reported. View BugCrunch report #152. |
4978 | Added the options to include all notes, exclude collapsed notes, or exclude all notes from print and PDF outputs. View BugCrunch report #459. |
5275 | Fixed an issue where zero-size ellipses and arcs were erroneously selected |
System Components: Soft Design System
5134 | Published Core Projects now include all vhdl files for Altera target. View BugCrunch report #791. |
5391 | FPGA_DELAY_MAX, FPGA_DELAY_MAX_TO and FPGA_DELAY_FROM handling has been improved. Bus values are correctly passed to UCF file. View BugCrunch report #512. View BugCrunch report #567. |
System Components: Soft Design Support
5134 | Published Core Projects now include all vhdl files for Altera target. View BugCrunch report #791. |
5264 | Wishbone interconnect has been improved. Multicycle peripherals are handled correctly. |
FPGA Components: Instrument - Digital IO
1668 | DigitalIO ports are correctly named when more than 26 ports are added. Port names are valid hdl identifiers and are not causing build errors. |
Importers and Exporters: Importer - CADSTAR
3650 | The CADSTAR importer has been fixed so that it can now handle invalid characters in sheet filenames. |
Importers and Exporters: Importer - PADS
4863 | PADS plane and mixed signal/plane layer types are now detected more reliably and initialized in the layer map as internal plane layers, when appropriate. |
5419 | Removed indication from dialogs that all used PADS layers must be mapped, as this is no longer required. |
5435 | Part decals that include pieces of type 'TAG' are now properly read by the PADS Importer, and cease to ultimately cause access violations. |
5443 | Pcb design import now creates solid regions on plane layers to produce copper void areas where appropriate. |
Output Generators: Output - ERC
4530 | No ERC Directives in schematic have been enhanced and can now suppress specific violations. Only the selected warning or error conditions are suppressed and any other warning or error will be detected and reported. View BugCrunch report #152. |
Output Generators: Output - NC-Drill
5404 | A new option was added to NCDrill Settings dialogue that will allow the user to output the EIA Binary Drill file or not. The default for this option is to not generate this NCDrill output type. View BugCrunch report #706. |
Output Generators: Output - STEP
5405 | Fixed issue where PcbDoc with circular holes exported as STEP would load incorrectly into Catia. View BugCrunch report #328. |
Output Generators: Printer - Schematic
4530 | No ERC Directives in schematic have been enhanced and can now suppress specific violations. Only the selected warning or error conditions are suppressed and any other warning or error will be detected and reported. View BugCrunch report #152. |