How Design Rules are Applied
Different design rules are applied in different situations. Certain rules can be applied as you design, by enabling the online design rule check (DRC) feature. A violation of a rule is flagged as soon as the violation occurs during placement. You may prefer to design first and check for violations later. If this is the case, you could enable the batch DRC feature, which will apply a certain set of rules when launched and provide feedback via a report. Some rules are only applied at certain times and during software operations, such as autorouting, autoplacement and manufacturing output generation.The PCB Editor only applies each rule when it is appropriate. A rule's definition specifies when that particular rule is applied. To reiterate, each rule is applied in one or more of the following situations:
- Online Design Rule Check (DRC) : running in the background, as you work, flagging and/or automatically preventing design rule violations of certain rule types
- Batch DRC : allows you to manually run a DRC at any time during the board design process, on all enabled rule types, and obtain a report
- During a software operation : certain rules are monitored during a software operation including: polygon pour, autorouting, autoplacement and output generation. Examples of these include the mask expansion rule which is monitored during output generation and the routing via style rule which is monitored during autorouting.
The following table summarises where each of the individual rule types are applied:
Rule | Category | Autorouter | Online DRC | Batch DRC | Output Generation | Other |
Clearance | Electrical | ✔ | ✔ | ✔ | Interactive routing, Polygon placement | |
Short-Circuit | Electrical | ✔ | ✔ | |||
Un-Routed Net | Electrical | ✔ | ✔ | |||
Un-Connected Pin | Electrical | ✔ | ||||
Modified Polygon | Electrical | ✔ | ✔ | |||
Width | Routing | ✔ | ✔ | ✔ | Interactive routing | |
Routing Topology | Routing | ✔ | ||||
Routing Priority | Routing | ✔ | ||||
Routing Layers | Routing | ✔ | ✔ | (since AD10 SP14 for Online DRC) | ||
Routing Corners | Routing | Third party Autorouters (e.g. Specctra) | ||||
Routing Via Style | Routing | ✔ | Interactive routing | |||
Fanout Control | Routing | ✔ | Interactive routing | |||
Differential Pairs Routing | Routing | ✔ | ✔ | Interactive routing | ||
SMD To Corner | SMT | ✔ | ✔ | Interactive Routing | ||
SMD To Plane | SMT | ✔ | ✔ | |||
SMD Neck-Down | SMT | ✔ | ✔ | |||
SMD Entry | SMT | ✔ | ✔ | Interactive Routing | ||
Solder Mask Expansion | Mask | ✔ | ||||
Paste Mask Expansion | Mask | ✔ | ||||
Power Plane Connect Style | Plane | ✔ | Internal Planes | |||
Power Plane Clearance | Plane | ✔ | Internal Planes | |||
Polygon Connect Style | Plane | Polygon placement | ||||
Broken plane | Plane | ✔ | Additional split plane error report | |||
Dead Copper | Plane | ✔ | Additional split plane error report | |||
Starved Thermal | Plane | ✔ | Additional split plane error report | |||
Fabrication and Assembly Testpoint Style | Testpoint | ✔ | ✔ | ✔ | ✔ | Testpoint Manager |
Fabrication and Assembly Testpoint Usage | Testpoint | ✔ | ✔ | ✔ | ✔ | Testpoint Manager |
Minimum Annular Ring | Manufacturing | ✔ | ✔ | |||
Acute Angle | Manufacturing | ✔ | ✔ | |||
Hole Size | Manufacturing | ✔ | ✔ | |||
Layer Pairs | Manufacturing | ✔ | ✔ | Interactive routing | ||
Hole To Hole Clearance | Manufacturing | ✔ | ✔ | |||
Minimum Solder Mask Sliver | Manufacturing | ✔ | ✔ | |||
Silk To Solder Mask Clearance | Manufacturing | ✔ | ✔ | |||
Silk To Silk Clearance | Manufacturing | ✔ | ✔ | |||
Net Antennae | Manufacturing | ✔ | ✔ | |||
Silk To BoardRegion Clearance | Manufacturing | ✔ | ✔ | |||
Board Outline Clearance | Manufacturing | ✔ | ✔ | ✔ | Interactive routing | |
Parallel Segment | High Speed | ✔ | ✔ | |||
Length | High Speed | ✔ | ✔ | |||
Matched Lengths | High Speed | ✔ | ✔ | Equalize Net Lengths command | ||
Daisy Chain Stub Length | High Speed | ✔ | ✔ | |||
Vias Under SMD | High Speed | ✔ | ✔ | |||
Maximum Via Count | High Speed | ✔ | ✔ | |||
Room Definition | Placement | ✔ | ✔ | Arrange Within Room command | ||
Component Clearance | Placement | ✔ | ✔ | Autoplacement (Cluster Placer) | ||
Component Orientations | Placement | Autoplacement (Cluster Placer) | ||||
Permitted Layers | Placement | Autoplacement (Cluster Placer) | ||||
Nets to Ignore | Placement | Autoplacement (Cluster Placer) | ||||
Height | Placement | ✔ | ✔ | Autoplacement PCB3D Editor | ||
Signal Stimulus | Signal Integrity | ✔ | Signal Integrity Analysis | |||
Overshoot - Falling Edge | Signal Integrity | ✔ | Signal Integrity Analysis< | |||
Overshoot - Rising Edge | Signal Integrity | ✔ | Signal Integrity Analysis | |||
Undershoot - Falling Edge | Signal Integrity | ✔ | Signal Integrity Analysis | |||
Undershoot - Rising Edge | Signal Integrity | ✔ | Signal Integrity Analysis | |||
Impedance | Signal Integrity | ✔ | Signal Integrity Analysis | |||
Signal Top Value | Signal Integrity | ✔ | Signal Integrity Analysis | |||
Signal Base Value | Signal Integrity | ✔ | Signal Integrity Analysis | |||
Flight Time - Rising Edge | Signal Integrity | ✔ | Signal Integrity Analysis | |||
Flight Time - Falling Edge | Signal Integrity | ✔ | Signal Integrity Analysis | |||
Slope - Rising Edge | Signal Integrity | ✔ | Signal Integrity Analysis | |||
Slope - Falling Edge | Signal Integrity | ✔ | Signal Integrity Analysis | |||
Supply Nets | Signal Integrity | ✔ | Signal Integrity Analysis |