PB03 Resources - USB Port

The PB03 provides a USB 2.0 port, identical to that found on the NB2DSK01 motherboard. The port is provided courtesy of a USB B-type connector.

Figure 1. USB 2.0 interface port.

Providing the high-speed interface between a processor in an FPGA design and the USB bus is an EZ-USB SX2™ device (CY7C68001-56LFC, from Cypress Semiconductor). This device has a built-in USB transceiver and a Serial Interface Engine (SIE), which automatically manages the USB protocol. Powered by the PB03's 3.3V supply, it supports Full (12Mbps) or High (480Mbps) speed operation.

Although the device is configured to provide a 16-bit bidirectional data bus, only the low-order byte (USB_D[7..0]) is used for communications with the processor.

Internal clocking for the USB transceiver (and various internal logic) is supplied from an internal PLL, which itself is driven by an external 24MHz crystal connected across the device's XTALIN and XTALOUT pins.

Reset of the USB interface device is provided through use of a supervisory reset circuit device – a MAX6315US26D1, from Maxim. This device will assert the reset signal to the CY7C68001 (active Low) if its 3.3V supply voltage dips below 2.3V, or if it receives an external reset signal from the processor in the FPGA design. The reset signal will remain asserted for a minimum of 1ms (typically 1.4ms) after the supply voltage rises above this threshold, and/or the processor deasserts its reset signal.

The USB data lines (D+, D-) are protected against high transient voltages through the use of a low-capacitance transient voltage suppressor device – a NUP2201MR6, from ON Semiconductor.

Figure 2. USB high-speed interface
device (U7_US), voltage suppressor
(U13_US), supervisory reset device
(U16_US) and 24MHz crystal (Y1_US).

Location on Board

The USB connector (designated J1) is located toward the lower-right corner, on the component side of the board – to the right of the IrDA interface.

The CY7C68001 device (designated U7_US), the NUP2201MR6 device (designated U13_US) and the MAX6315 device (designated U16_US) are also located on the component side of the board, above the USB port itself.

The 24MHz crystal (designated Y1_US) is located on the component side of the board, to the bottom-left of the CY7C68001 device.

Schematic Reference

The USB circuitry can be found on the following sheets of the peripheral board schematics:

• USB_CY7C68001-56LFC.SchDoc (entitled High-Speed USB 2.0 Controller)

• CON_USBB_RA.SchDoc (entitled USB 2.0 Type B Connector).

Design Interface Component

Table 1 summarizes the available design interface component that can be placed from the FPGA PB03 Port-Plugin.IntLib to access the USB interface.

Further Device Information

For more information on the CY7C68001 device, refer to the datasheet (CY7C68001.pdf) available at www.cypress.com.

For more information on the MAX6315 device, refer to the datasheet (MAX6315.pdf) available at www.maxim-ic.com.

For more information on the NUP2201MR6 device, refer to the datasheet (NUP2201MR6-D.pdf) available at www.onsemi.com.