PB02 Resources - SD Card Reader

Frozen Content

Modified by Admin on Sep 13, 2017

The Secure Digital (SD) memory card is among a host of such cards available in today's world of storage-hungry devices, such as PDAs and digital cameras. The PB02 provides a reader for this type of memory card, by way of a DM1B-DSF-PEJ connector (HRS6090003-5), from Hirose.

Figure 1. Secure Digital (SD) memory card
reader.

The PB02 comes supplied with a 512MB SD card.

The connector features a push-in/push-out ejection mechanism, locking the SD card firmly in place. Should you accidentally pull the card free from the connector (using moderate force), the ejection mechanism will not be damaged.

The connector provides Card Detection and Write Protection switches, to flag whether a card has been inserted, and the write status of that card. Both switches are commoned to the PB02's 3.3V power supply and are normally open (i.e. when no card is inserted). When a card is inserted:

The Card Detection switch will close.

The Write Protection switch will close only if the SD card is enabled for writing to. If the card's write protect tab is in the 'Locked' position (typically down) the card is Read Only and the Write Protection switch will remain open.

In each case, switch closure will result in a logical '1' being sent to the daughter board FPGA on corresponding signal lines SD_DETECT and SD_PROTECT, respectively.

All I/O signals relating to the SD card are made available to the daughter board FPGA. Although SD cards support three modes of data transfer – SD (1-bit), SD (4-bit) and SPI – only the 4-wire SPI mode is readily supported through use of an intermediate SD Card Controller. This peripheral is placed in the FPGA design and sits between a processor in the design and the SD card reader on the PB02.

Table 1 summarizes the pinout of an SD card and the signals made available to the daughter board FPGA. The table highlights in grey those signals that relate to use of the card in the SPI mode of data transfer.

Table 1. Use of SD card signals.

Pin	Signal Function in SD mode	Signal Function in SPI mode	Signal arriving at Daughter Board...
1	Data Line 3	Chip Select	`SD_DAT3`
2	Command Line	Master Out	`SD_CMD`
3	Ground	Ground	-
4	Voltage Supply	Voltage Supply	-
5	Clock	Clock	`SD_CLK`
6	Ground	Ground	-
7	Data Line 0	Master In	`SD_DAT0`
8	Data Line 1	Unused	`SD_DAT1`
9	Data Line 2	Unused	`SD_DAT2`

Should you wish to use the SD card's 1-bit SD mode, where data is transferred over the SD_DAT0 line, you will need to create your own SD Controller, which would reside in the FPGA design. The same applies to use of the card's 4-bit SD mode, where data is transferred in parallel over all four data lines.

An additional signal from the FPGA design – LED_ACTIVE – can be used to indicate when the host processor in the design is accessing the SD card. Taking this line High will result in the LED at the top-right of the board (labeled 'HDD ACTIVE' and designated LED1) becoming lit (Red).

Location on Board

The SD card reader (designated SD1) is located at the bottom of the board, on the solder side.

The 'HDD ACTIVE' (LED1) LED is located on the component side, toward the top-right corner of the board.

Figure 2. HDD activity LED
(LED1).

Schematic Reference

The SD card reader circuitry can be found on sheet CON_SD_HIROSE_609_0003_5.SchDoc (entitled SD-CARD HIROSE 609_0003_5) of the peripheral board schematics.

Design Interface Component

Table 2 summarizes the available design interface component that can be placed from the FPGA PB02 Port-Plugin.IntLib for access to, and communications with, an SD memory card.

Table 2. SD card reader port-plugin component.

Component Symbol	Component Name	Description
	`SD_CARD`	Place this component to interface to the Secure Digital (SD) card reader and write/read an SD memory card inserted within. Note: Although the data lines are truly bidirectional, this interface component reflects use of the card in SPI mode only, with `SD_DAT0` used as input only (for data read from the card) and `SD_DAT3` used as output only (for chip select).

The following signals, although not part of the port component, are made available to the daughter board FPGA:

SD_DAT1

SD_DAT2

To access these signals and use them in a design, you will need to place ports appropriately mapped to the device pins on which these signals arrive.

Should you wish to use the 'HDD ACTIVE' LED, you will need to place the relevant design interface component, as summarized in Table 3.

Table 3. 'HDD ACTIVE' LED port-plugin component.

Component Symbol	Component Name	Description
	`LED_ACTIVE`	Place this component to interface to the `'HDD ACTIVE'` LED on the board.

Further Device Information

For more information on the DM1B-DSF-PEJ connector, refer to the datasheet (e60900048.pdf) available at www.hirose-connectors.com.