PB01 Resources - Video Input Capture

The PB01 supports the connection of external NTSC or PAL analog video signals. Both Composite Video and S-Video inputs are supported:

• Connection of a Composite Video signal is made through two RCA phono jacks, designated J5 and J6, which cater for the Luma (luminance or intensity) and Chroma (chrominance or color) components of the signal respectively.
   
  
  Figure 1. Composite Video input
  jacks.
   
• Connection of an S-Video signal is made through a 4-way mini-DIN (Female) connector, designated J4.
   
  
  Figure 2. S-Video input connector.

The analog video input is converted into 8-bit digital YCbCr 4:2:2 component video, through use of a TVP5150AM1 video decoder device (from Texas Instruments). The decoder is powered by the PB01's 1.8V and 3.3V supplies.

Figure 3. TVP5150AM1 Video
Decoder device.

The decoder provides a 9-bit ADC, with sampling carried out in accordance with the ITU-R BT.601 recommendation. This recommendation defines the scheme for encoding interlaced analog video signals – for both 625 and 525 line systems – in digital form.

The sampling frequency is 27MHz, supplied from an internal PLL, which itself is driven by a 14.31818MHz signal connected to the decoder's XTAL1/OSC input pin. This signal – MHZ_14_3 – is sourced from a dedicated crystal oscillator (designated X1) which is used to provide the F4SC clock input to an AD725 device, when encoding an NTSC signal for video output (see PB01 Resources - Video Output). A test point (TP2) is available for verification of this frequency.

An additional reset signal is wired to the decoder's RESETB input. The decoder's Power Down (PDN) pin is tied high (to the 3.3V supply), preventing the powerdown feature, but allowing reset of the decoder to be brought under control of this reset signal. This signal is active Low and is sourced from the output of a supervisory reset circuit device – a MAX6315US26D1, from Maxim. This device will assert the reset signal to the TVP5150AM1 if its 3.3V supply voltage dips below 2.3V, thereby providing power-up reset of the decoder. The reset signal will remain asserted for a minimum of 1ms (typically 1.4ms) after the supply voltage rises above this threshold. When the reset signal is activated, all internal registers are reset and the decoder's internal processor is restarted.

Digital Video Format

The converted digital video stream can be output in one of two formats:

• 8-bit ITU-R BT.656 interface, with embedded synchronization

• 8-bit 4:2:2 YCbCr, with discrete synchronization signals.

By default, the TVP5150AM1 is configured to output digital video in the ITU-R BT.656 format and this is the format expected by a BT656 Controller used within an FPGA design.
 

 
The BT656 Controller takes as input the following output signals from the TVP5150AM1:

• VIDIN_DATA[7..0] – ITU-R BT.656-compliant video data stream

• VIDIN_PCLK – the pixel clock, fixed at 27MHz and used to clock the output video data stream. The pixel clock output from the TVP5150AM1 is passed through an intermediate zero-delay buffer (a CY2305 device, from Cypress Semiconductor).
   
  
  Figure 4. Zero-delay buffer device,
  from which the VIDIN_PCLK signal
  is obtained.
   
• VIDIN_INTERQ_GPLC – used to indicate the vertical blanking interval of the video data stream.

It decodes the BT.656-formatted video and reformats it into a simple memory image for storage in external video memory.

The following additional discrete synchronization signals are also made available to the daughter board FPGA:

• VIDIN_AVID – active video indicator

• VIDIN_HSYNC – horizontal synchronization signal

• VIDIN_VSYNC – vertical synchronization signal

• VIDIN_FID_CLCO – odd/even field indicator.

These signals are made available should you wish to use the alternate output format in your design (non-ITU-R BT.656), though in doing so, you will need to create your own video interface controller, attached as peripheral I/O to a processor in the FPGA design.

Configuring/Controlling the Decoder

The video decoder is controlled by a processor within the FPGA design, over the I2C bus. The decoder (an I2C Slave) is controlled through an intermediate I2C Controller (the I2C Master, also resident within the FPGA design). The following are the addresses that must be used by a processor to write and read the TVP5150AM1 device over the I2C bus. Each address is made up of a 7-bit actual address for the device and an additional bit (LSB) to distinguish whether the I2C Master is writing to ('0'), or reading from ('1') that device.

• I2C Write Address – B8h (10111000)

• I2C Read Address – B9h (10111001)

 
Refer to the datasheet for the TVP5150AM1 for details of internal registers and respective settings used to configure the decoder.

Location on Board

The Composite Video input jacks – 'Input A' (designated J5) and 'Input B' (designated J6) are located on the component side of the board, to the right of the S-Video I/O connectors.

The S-Video input connector – labeled 'Input' and designated J4 – is also located on the component side of the board, towards the top-left corner.

The TVP5150AM1 device (designated U7) is located on the solder side of the board.

The zero-delay buffer device (designated U4) is located on the component side of the board, below the Composite Video output jack.

The MAX6315 device (designated U1T) is located on the component side of the board, to the top-left of the CS4270 audio CODEC device (U1AC).

Figure 5. Supervisory reset
device, MAX6315.

The 14.31818MHz crystal oscillator (X1) is located on the component side of the board, to the top-right of the board's test points.

The test point for the 14.31818MHz oscillator output (TP2) is located to the left of the 17.734475MHz crystal oscillator (X2).

Figure 6. Crystal oscillators (X1 and X2) and associated
test points.

Schematic Reference

The video input circuitry can be found on the following sheets of the peripheral board schematics:

• PB01_VIDEO_IN.SchDoc (entitled Video Input)

• VIDEO_IN_TVP5150.SchDoc (entitled Video Input)

The MAX6315 device can be found on sheet PB01_Top.SchDoc (entitled Top Level). The 14.31818MHz crystal oscillator can be found on sheet VIDEO_OSCILLATOR.SchDoc (entitled Video Oscillator).

Design Interface Component

Table 1 summarizes the available design interface component that can be placed from the FPGA PB01 Port-Plugin.IntLib for access to, and communications with, the TVP5150AM1 device.

To enable a host processor in your FPGA design to control operation of the TVP5150AM1 device, you will need to place the relevant design interface component that allows communications with the video decoder device over the I2C bus, as summarized in Table 2.

If your design involves communications with multiple I2C-compatible devices, you will need to place the generic I2C_BUS device. For more information, see Using Multiple SPI and I2C Devices in a Design.

Further Device Information

For more information on the TVP5150AM1 device, refer to the datasheet (tvp5150am1.pdf) available at www.ti.com.

For more information on the MAX6315 device, refer to the datasheet (MAX6315.pdf) available at www.maxim-ic.com.

For more information on the CY2305 device, refer to the datasheet (cy2305_cy2309_8.pdf) available at www.cypress.com.