EP3C40F780C8N - Supported Psueudo-Differential IO Standards
The following table lists the pseudo-differential I/O standards supported by the EP3C40F780C8N device. Pseudo-differential outputs involve using two single-ended outputs, with the second inverted. Pseudo-differential inputs simply treat differential inputs as single-ended inputs, with only one input being decoded.
Table 1. Supported pseudo-differential I/O standards.| I/O Standard | Description |
|---|---|
Differential HSTL-12 class I | Differential High-Speed Transceiver Logic (1.2V) Class I |
Differential HSTL-12 class II | Differential High-Speed Transceiver Logic (1.2V) Class II |
Differential HSTL-15 class I | Differential High-Speed Transceiver Logic (1.5V) Class I |
Differential HSTL-15 class II | Differential High-Speed Transceiver Logic (1.5V) Class II |
Differential HSTL-18 class I | Differential High-Speed Transceiver Logic (1.8V) Class I |
Differential HSTL-18 class II | Differential High-Speed Transceiver Logic (1.8V) Class II |
Differential SSTL-18 class I | Differential Stub Series Terminated Logic (1.8V) Class I |
Differential SSTL-18 class II | Differential Stub Series Terminated Logic (1.8V) Class II |
Differential SSTL-2 class I | Differential Stub Series Terminated Logic (2.5V) Class I |
Differential SSTL-2 class II | Differential Stub Series Terminated Logic (2.5V) Class II |
For detailed information, refer to the Cyclone III Device Handbook (cyclone3_handbook.pdf) available at www.altera.com.