Downloading a Test Project to the NanoBoard 3000

Frozen Content

To ensure that Altium Designer and the NanoBoard 3000 are installed and functioning correctly, follow the steps below to process an example project, from within Altium Designer, and download it to the User FPGA resident on the NanoBoard. For this test we will use the NB3000_Bouncing_Balls.PrjFpg example project, found in the \Examples\Soft Designs\Display\NB3000 Bouncing Balls folder of the installation.
 

The User FPGA on the NanoBoard 3000 is programmed with an example Slide-Show design on power-up. This design (including embedded software) is stored as a .bin file in serial Flash memory. The Devices view will therefore show the physical device as being Programmed and the Soft Devices chain will show a TSK3000A processor as Running.

Although not necessary, before getting started with downloading a different test project, we will first reset the physical device – the User FPGA on the NanoBoard 3000 – thereby starting with the device in an 'un-programmed' state.

  1. Access the Devices view (View»Devices View).
     
  2. Right-click on the icon for the physical FPGA device, in the Hard Devices chain, and choose Reset Hard Device from the context menu that appears.
     

    Apppearance of the Devices view after resetting the physical device.


     

  3. Select File»Open Project.
     
  4. Navigate to the \Examples\Soft Designs\Display\NB3000 Bouncing Balls directory and open the file NB3000_Bouncing_Balls.PrjFpg. When the project has loaded, the Projects panel on the left side of the workspace will display the files in this project.
     
  5. In the Devices view, you will notice that the open project is automatically assigned to the User FPGA device on the NanoBoard 3000.
     

    The design is automatically targeted to the User FPGA device.


     
    This assignment takes place because a valid configuration exists for the project, containing a constraint file that targets the User FPGA device, as illustrated by a valid project/configuration entry in the field below the icon for the physical device. If a compatible configuration did not exist, you would need to run the auto-configuration feature to quickly create one.
     

  6. The four stages displayed above the physical device are its Process Flow. To process the project and download it to the User FPGA device, click the Program FPGA button – the final stage in this flow.
     

    Starting the programming process.


     
    The system will sequentially invoke each stage of the Process Flow. This involves:
     
    ~  Compiling the source project files
    ~  Synthesizing the design
    ~  Calling the vendor place and route tools to process the design for the target FPGA, and
    ~  Downloading the design to the User FPGA.
     
    This process can take several minutes depending on the speed of your computer and the specific target device on the 3000-series NanoBoard you are using.
     

    Reaching the Place and Route stage of the overall Build process.

    If the system fails during the Build processes, shown by a magenta status indicator, this can be because the FPGA vendor toolsare not correctly installed or have not been properly activated. Please refer to the information supplied with the FPGA vendor tools for information on installing and activating these tools.


Once the design has been downloaded all of the stage indicators in the Process Flow will be green, the text underneath the physical device's icon will change from Reset to Programmed, and the Results Summary dialog will be shown. On the software side, this indicates that the project has been successfully processed and downloaded to the User FPGA. Close this dialog.

Physical device successfully programmed with the FPGA design.

On the hardware side, the 'PGM' LED on the motherboard – to the right of the TFT LCD panel – will be lit (Yellow), confirming that the design has been loaded into the physical device. For this example project, additional confirmation of successful programming comes in the form of bouncing balls displayed on the TFT LCD panel.

Bouncing balls! - indication that the design has been
programmed into the User FPGA.

Using the supplied stylus, touch and hold anywhere on the screen – the four balls will stack at that point, largest to smallest with the smallest on top. Take the stylus away to let the balls resume bouncing.

Also notice that the lower chain in the Devices view – the Soft Devices chain – becomes populated with any soft (Nexus-enabled) devices detected in the design. This example project contains a single 32-bit processor (a TSK3000A). The icon representing the processor is shown as 'Running'. This reflects that the system is communicating with this processor, allowing you to interact and control the processor for development and debugging purposes. Double-clicking on the icon for any soft (Nexus-enabled) device in this chain (processors, virtual instruments) will give access to the front panel for that device.

Example of accessing the controls for a soft JTAG device (TSK3000A processor).

See Also

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