Daughter Board Common-Bus SRAM

The daughter board includes Static RAM as part of the common-bus block of memory resources available to the FPGA.

The SRAM is provided in the form of two 4Mbit, high-speed CMOS SRAM devices. Each device is organized as 256K x 16 bits – combined together to give 256K x 32-bit storage (1MByte). Both devices are powered by the daughter board's 3.3V supply.

Although the devices require 18 address lines (SRAM_A[19..2]), the common bus interface makes provision for a nineteenth address line (SRAM_A20), giving the daughter board the flexibility to accommodate 512 x 16-bit devices, should they require to be fitted.

Location on Board

The common-bus SRAM device on the component side of the board is located above the power supply test points, and to the right of the common-bus SDRAM device.

Figure 1. Common-bus SRAM on the
component side (as seen on the DB30).

The common-bus SRAM device on the solder side of the board is located towards the top-left corner of the board, and to the left of the common-bus SDRAM device.

Figure 2. Common-bus SRAM on the solder
side (as seen on the DB30).

Schematic Reference

The common-bus SRAM devices can be found on sheet SRAM_256Kx32_TSOP44_1.SchDoc (entitled 256K x 32 SRAM - TSOP44 x 2) of the daughter board schematics.

The common-bus memory block and interface wiring can be found on sheet NB2_CommonMemory.SchDoc (entitled Common-Bus Memory Block).