WB_FPU - Internal Units

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Modified by Admin on Nov 6, 2013

The following sections detail the various units that constitute the WB_FPU.

Denormalization Units

Denormalized numbers themselves are not supported in the WB_FPU. However, for the purposes of calculation, it is necessary to internally perform a light form of denormalization. The Denormalization Unit takes an IEEE 754-formatted floating-point number and splits it into a "float" typed signal containing the following information bits:

NaN, Infinity and Zero bits - indicating special values

1-bit Sign

10-bit Exponent

24-bit Significand – consisting the implicit or hidden bit as the MSB, followed by the fraction

Guard and Sticky bits – used as an aid in rounding.

The exponent in the denormalized value is still biased. This avoids the need for extra hardware to perform bias handling in both Denormalization and Normalization units.

The internal representation of the exponent has two extra bits – MSB and MSB-1 – both of which are initially set to '0'. These bits are used to facilitate easy detection of exponent underflow and overflow in the calculation units.

When the Denormalization Unit has finished constructing the internal float value it will set a ready flag, to indicate that this value is ready for further processing.

Two Denormalization Units are included, for operand A and operand B respectively. Each unit takes its input directly from the Wishbone interface (on the DAT_I bus), provided a write to the corresponding operand address (1h for OPA and 2h for OPB) is being performed.

Conversion Units

The WB_FPU contains two conversion units – one for floating-point-to-integer (FTOI) conversion and one for integer-to-floating-point (ITOF) conversion.

The ITOF Unit takes its input (a 32-bit integer value) directly from the Wishbone interface (on the DAT_I bus), provided a write to the OPA address (1h) is being performed. The unit generates an internal float-typed signal and a ready signal – to signal the subsequent Normalization Unit that the converted value is ready for processing.

The FTOI Unit takes its input (an internal float-typed value) from the Denormalization Unit associated with OPA, which in turn takes its input (an IEEE 754-formatted floating-point value) directly from the Wishbone interface (on the DAT_I bus), provided a write to the OPA address (1h) is being performed. The unit converts the float-typed value to a 32-bit integer and generates a ready flag – to signal that the converted value is ready for transfer over the Wishbone interface.

Addition Unit

The Addition Unit is able to add two IEEE 754 floating-point values (OPA and OPB) without taking signs into account.

The unit takes its operand inputs from the Denormalization Units. The result of the addition may have Guard and Sticky bits set for rounding purposes, and the special value bits (NaN, Infinity, Zero) will be updated if required. Once the calculation is complete a ready flag will be set, to signal the subsequent Normalization Unit that a new value is ready.

The resulting Sign bit will be that of OPA.

Since addition is performed without regard for sign, operands with different signs should be subtracted rather than added. When reading the result of an addition (reading address 2h) featuring operands of equal sign, the normalized result from the Addition Unit will be obtained. When the signs differ, the normalized result from the Subtraction Unit will be obtained instead.

Subtraction Unit

The Subtraction Unit is able to subtract two IEEE 754 floating-point values (OPA and OPB) without taking signs into account. The smaller value is always subtracted from the larger.

The unit takes its operand inputs from the Denormalization Units. The result of the subtraction may have Guard and Sticky bits set for rounding purposes, and the special value bits (NaN, Infinity, Zero) will be updated if required. Once the calculation is complete a ready flag will be set, to signal the subsequent Normalization Unit that a new value is ready.

The resulting Sign bit will depend on the initial operand values:

If OPA < OPB, then the resulting Sign bit will be the inverse of the original Sign bit for OPA

If OPA > OPB, then the resulting Sign bit will be that of OPA.

Since subtraction is performed without regard for sign, operands with different signs should be added rather than subtracted. When reading the result of a subtraction (reading address 3h) featuring operands of equal sign, the normalized result from the Subtraction Unit will be obtained. When the signs differ, the normalized result from the Addition Unit will be obtained instead.

Multiplication Unit

The Multiplication Unit multiplies two IEEE 754 floating-point values (OPA and OPB).

The unit takes its operand inputs from the Denormalization Units. The result of the multiplication may have Guard and Sticky bits set for rounding purposes, and the special value bits (NaN, Infinity, Zero) will be updated if required. Once the calculation is complete a ready flag will be set, to signal the subsequent Normalization Unit that a new value is ready.

Division Unit

The Division Unit divides two IEEE 754 floating-point values (OPA by OPB).

The unit takes its operand inputs from the Denormalization Units. The result of the division may have Guard and Sticky bits set for rounding purposes, and the special value bits (NaN, Infinity, Zero) will be updated if required. Once the calculation is complete a ready flag will be set, to signal the subsequent Normalization Unit that a new value is ready.

Division is not a ready-to-use operational block in VHDL. Therefore a successive approximation algorithm has been implemented that determines one bit of the significand per cycle of CLK_I. As a result, the floating-point division operator is slower in comparison to the other operators.

Normalization Units

The Normalization Unit takes as input an internally-formatted float-typed number and constructs the corresponding IEEE 754-formatted floating-point value. The value will be rounded in accordance with the significand LSB, the Guard and Sticky bits. Once construction of the IEEE 754 floating-point value is complete, the unit generates a ready flag – to signal that the value is ready for transfer over the Wishbone interface.

Effect of Special Bits

The special value bits of the input number (NaN, Infinity, Zero) are checked, with the following influence on the resulting IEEE 754 floating-point value:

If the NaN bit of the input value is '1', then the Sign of the resulting IEEE 754 float will be set to '0' and all other bits (30..0) set to '1'.
If the Infinity bit is '1', then the Sign of the IEEE 754 float will be set to that of the input number, the Exponent will be set to all '1's and the Significand set to all '0's.
If the Zero bit of the input value is '1', then the Sign of the IEEE 754 float will be set to that of the input number and all other bits (30..0) set to '0'.

Exponent Underflow and Overflow Detection

As mentioned previously, the internal representation of the exponent has two extra bits – MSB and MSB-1 – both of which are used to facilitate easy detection of exponent underflow and overflow in a calculation unit. Detection is as follows:

If MSB of exponent is '1', the resulting exponent underflows and the IEEE 754 floating-point number returned will be rounded to zero by the Normalization Unit (i.e. all exponent and significand bits set to '0').

If MSB of exponent is '0' but MSB-1 is '1', the resulting exponent overflows and the IEEE 754 floating-point number returned will be rounded to infinity by the Normalization Unit (i.e. all exponent bits set to '1' and all significand bits set to '0').