Mapping the FPGA Design to the Device Pins

Frozen Content

Mapping is a method by which your design can be interfaced to the physical pins of the FPGA device in which it is programmed. Put another way, it is the means by which your design can interact with the 'outside world'. By mapping internal digital signals to the device pins, your logic is able to communicate to other areas of your product. As part of this mapping, you would also define analog characteristics of the pins, such as IO standards, drive strengths and slew rates.

In Altium Designer, this mapping is achieved using ports (or port components), configurations and constraint files. An FPGA design can have multiple defined configurations, with each configuration containing the constraint files (pin mappings, clock constraints, place and route constraints) required to target a different physical device.

Figure 1. Targeting a design to a physical device on a daughter board plugged into the Desktop NanoBoard. The example mapping illustrates a couple
of signals associated with a resource on a peripheral board and their subsequent mapping path to the physical pins of the target device.

Moving to a Custom Board

Once you have your FPGA design (and associated embedded software for any processors) running 'bug-free' on a Desktop NanoBoard, it is time to consider how that design - your product - will be deployed in the field.

Altium provides a range of Deployment NanoBoards that you can either use entirely as an off-the-shelf solution or that you can customize with your own peripheral boards. Alternatively you can go for a fully custom PCB solution. The choice of deployment options will be influenced by a range of factors including cost, time to market, logistics, and form and fit constraints.

Figure 2. Move your product to the field using your own custom PCB or one of the available Deployment NanoBoard solutions.

See Also

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