Custom Logic Tutorial - Capturing the Design
Let's go ahead and capture our simple accumulator design in an FPGA project within Altium Designer.
- First, create a new FPGA project and save it with the name
CHC_Accumulator.PrjFpg, in a new folder calledC Custom Logic Tutorial.
- Add a new schematic document to this project and save the file with the name
CHC_Accumulator.SchDoc, in the same folder as the parent project.
Table 1 identifies the various logic components and design interface components that we need to use for our design, as well as the source integrated libraries in which they can be found.
Table 1. Design components required in the accumulator design schematic.
| Symbol | Component Name | Description | Library |
|---|---|---|---|
|
| CUSTOM_INSTRUMENT | Custom Instrument | FPGA Instruments.IntLib |
|
| CLOCK_REFERENCE | This component interfaces to the fixed 20MHz system clock signal on the Desktop NanoBoard. We will use this signal to provide the synchronous clock signal to our logic. | FPGA NB2DSK01 Port-Plugin.IntLib |
|
| TEST_BUTTON | This component interfaces to the 'DAUGHTER BD TEST/RESET' button on the Desktop NanoBoard. We will use this signal (inverted) to provide the reset signal for our custom logic. | FPGA NB2DSK01 Port-Plugin.IntLib |
|
| NEXUS_JTAG_CONNECTOR | This component interfaces to the Soft JTAG chain signals (NEXUS_TMS, NEXUS_TCK, NEXUS_TDI and NEXUS_TDO) and essentially 'brings' the chain into the design. | FPGA NB2DSK01 Port-Plugin.IntLib |
|
| NEXUS_JTAG_PORT | This component is used to 'wire' our Nexus-enabled custom instrument component into the Soft JTAG chain. | FPGA Generic.IntLib |
|
| FD32EB | 32-bit D Flip-Flop with clock enable, bus version. We will use this to latch the output value from our custom accumulation circuit (which is only available for 1 clock cycle). | FPGA Generic.IntLib |
|
| INV | Inverter. We will use this to invert the active-Low input from the 'DAUGHTER BD TEST/RESET' button. | FPGA Generic.IntLib |
- Go ahead and initially place these components as shown in Figure 1. Don't forget to designate the applicable components in the design (using, for example, the Tools » Annotate Schematics Quietly command).
Figure 1. Initial placement of components on the schematic sheet, CHC_Accumulator.SchDoc.
With the components initially placed, we now need to perform the following to fully complete the capture of our design: