Altera Nios II
The Nios II is a 32-bit Wishbone-compatible RISC processor, for use in FPGA designs targeting supported Altera families of physical FPGA devices.
Altium Designer currently supports use of the Nios II processor with the following Altera FPGA device families:
Cyclone®, Cyclone® II, Cyclone® III, Stratix®, Stratix® II, Stratix® III, Stratix® GX, Stratix® II GX.
The processor comes in three flavors – fast, standard and economy. Although each is placed in an Altium Designer-based FPGA project as a Nios II, this is essentially a Wishbone-compliant wrapper that allows use of Altera's corresponding 'soft' Nios II processor core.
All instructions are 32-bits wide and most execute in a single clock cycle (standard and fast variants only). In addition to fast register access, the Nios II features a user-definable amount of zero-wait state block RAM, with true dual-port access.
Only designs targeting supported Altera FPGA devices may make use of the processor. Should you wish the freedom of a both a device and FPGA Vendor-independent 32-bit system hardware platform, use the available TSK3000A 32-bit RISC processor.
Supply of these soft cores under the terms and conditions of the Altium End-User License Agreement does not convey nor imply any patent rights to the supplied technologies. Users are cautioned that a valid Nios II license from Altera is required for any use covered by such patent rights, including the implementation of this core in an Integrated Circuit or any other device. You will also need a licensed install of Altera's Quartus® II software. For further information:
Altium Designer currently supports versions 3.0 – 8.0 (inclusive) of the Altera Quartus II software and versions 5.1 – 8.0 (inclusive) of the Nios II processor core, available in the corresponding Altera Nios II Embedded Design Suite
- Pipelined RISC processor
- Nios2f: 6-stage pipeline
- Nios2s: 5-stage pipeline
- Nios2e: 1-stage pipeline
- Internal Harvard architecture
- Supports on-chip block RAM and/or external memory
- 4GByte address space (incorporating 2GByte of external address space)
- Wishbone I/O and memory ports for simplified peripheral connection
- Full Viper-based software development tool chain – C compiler/assembler/source-level debugger/profiler
- C-code compatible with other Altium Designer 8-bit and 32-bit Wishbone-compliant processor cores, for easy design migration.
Three variants of the Nios II processor core are available:
- Nios2f – "fast" variant, optimal for performance-critical applications and applications with large amounts of code and/or data (e.g. a system running a full-featured operating system). This variant has separate instruction and data caches. It provides the highest performance but is much larger in size.
- Nios2s – "standard" variant, optimal for cost-sensitive, medium-performance applications, including those with large amounts of code and/or data. This variant has an instruction cache, but no data cache. It provides a smaller-sized core, without sacrificing too much in the way of performance.
- Nios2e – "economy" variant, optimal for cost-sensitive applications, such as those found in the automotive and consumer industries. This variant has no instruction or data cache. It is around half the size of the Nios2s, but this comes at the expense of execution performance.
From an OpenBus System document, the Nios II processors can be found in the Processors region of the OpenBus Palette panel.
From a schematic document, all devices can be found in the FPGA 32-Bit Processors integrated library (
FPGA 32-Bit Processors.IntLib), located in the
\Library\Fpga folder of the installation.
32-bit Processor Fundamentals
Working with the Nios II
For detailed information about the hardware and functionality of the various Nios II processor core variants, including internal registers, block diagrams and interrupt handling, refer to the Nios II Processor Reference Handbook, available from www.altera.com/literature/lit-nio2.jsp. The Instruction Set Reference section of this guide provides detailed information with respect to the processor's instruction set, including instruction encoding and an alphabetical listing of all instructions by mnemonic.