FPGA Design

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This is the hardware design itself which will be programmed within the physical device. It will contain all of the logic and connectivity and typically feature a processor system.

There are three important phases to consider when creating your FPGA design:

  • Capture & Verification Phase – placing and wiring the 'ingredient' logic for the design and ensuring that it is free of electrical and drafting errors.
  • Configuration Phase – targeting the design to the physical device into which it is to be programmed (see Mapping the FPGA Design to the Device Pins).
  • Processing Phase – the job of turning the design from captured source files into a programming file that can be downloaded to the targeted device.

In Altium Designer, the design is created and managed within an FPGA project.

Design Components

In terms of design capture, a variety of FPGA-ready (and vendor-independent) components are supplied for use in your FPGA designs.

Figure 1. FPGA-ready components -- vendor-independent building blocks that enable designs to be created quickly and retargeted to alternate physical devices.

Processing

When it comes to processing the design, Altium Designer provides a central interface from where the design can be compiled, synthesized, built (using the appropriate and installed Vendor tools) and downloaded into the device.

Figure 2. Processing of an FPGA design within Altium Designer -- literally at the click of a button!

Working with Vendor Tools

Place and route, the process of implementing the design on the target silicon, requires an intimate understanding of the functionality and architecture of the device, a task best performed by software tools provided by the device vendor. The vendor software is operated by the Altium Designer environment, which automatically manages all project and file handling aspects required to generate the FPGA program file.

The vendor tools are integrated and accessed in the Altium Designer environment through the Devices view (View » Devices View) - specifically the Build phase of the Process Flow associated with the target physical FPGA device.

 

See Also

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